Part Number: SM470R1B1M-HT
Hello,
I started developing a firmware for the SM470r1B1M-HT microcontroller in IAR.
I'd like to use the interrupts of the SCI3 (this microcontroller has SCI1 and SCI3). They have to be mapped with the Interrupt Expansion Module.
I couldn't find too much documentation for this. In the iotms470r1b1m.h there are some possible mistakes.
Can you help me with this?
Regards,
Marius Raducanu
/***************************************************************************
**
** CIM interrupt channels
**
***************************************************************************/
#define CIM_SPI1 0 /* SPI1 end-transfer/overrun */
#define CIM_COMP2 1 /* COMP2 interrupt */
#define CIM_COMP1 2 /* COMP1 interrupt */
#define CIM_TAP 3 /* TAP interrupt */
#define CIM_SPI2 4 /* SPI2 end-transfer/overrun */
#define CIM_GIOA 5 /* GIO interrupt A */
/*#define CIM_RES 6 --- Reserved --- */
#define CIM_HET1 7 /* HET interrupt 1 */
#define CIM_I2C1 8 /* I2C1 interrupt */
#define CIM_SCIRXERR 9 /* SCI1 or SCI2 error interrupt */
#define CIM_SCI1RX 10 /* SCI1 receive interrupt */
/*#define CIM_RES 11 --- Reserved --- */
#define CIM_I2C2 12 /* I2C2 interrupt */
#define CIM_HECC1A 13 /* HECC1 interrupt A */
#define CIM_SCCA 14 /* SCC interrupt A */
/*#define CIM_RES 15 --- Reserved --- */
#define CIM_MIBADCEE 16 /* MibADC end event conversion */
#define CIM_SCI2RX 17 /* SCI2 receive interrupt */
#define CIM_DMA0 18 /* DMA interrupt 0 */
#define CIM_I2C3 19 /* I2C3 interrupt */
#define CIM_SCI1TX 20 /* SCI1 transmit interrupt */
#define CIM_SSI 21 /* SW interrupt (SSI) */
/*#define CIM_RES 22 --- Reserved --- */
#define CIM_HET2 23 /* HET interrupt 2 */
#define CIM_HECC1B 24 /* HECC1 interrupt B */
#define CIM_SCCB 25 /* SCC interrupt B */
#define CIM_SCI2TX 26 /* SCI2 transmit interrupt */
#define CIM_MIBADCE1 27 /* MibADC end Group 1 conversion */
#define CIM_DMA1 28 /* DMA Interrupt 1 */
#define CIM_GIOB 29 /* GIO interrupt B */
#define CIM_MIBADCE2 30 /* MibADC end Group 2 conversion */
#define CIM_SCI3 31 /* SCI3 error interrupt */
/***************************************************************************
**
** IEM interrupt channels
**
***************************************************************************/
/*#define IEM_RES 32 --- Reserved --- */
/*#define IEM_RES 33 --- Reserved --- */
/*#define IEM_RES 34 --- Reserved --- */
/*#define IEM_RES 35 --- Reserved --- */
/*#define IEM_RES 36 --- Reserved --- */
/*#define IEM_RES 37 --- Reserved --- */
#define IEM_HECC2A 38 /* HECC1 interrupt B */
#define IEM_HECC2B 39 /* HECC1 interrupt B */
#define IEM_SCI3RX 40 /* SCI2 receive interrupt */
#define IEM_SCI3TX 41 /* SCI1 transmit interrupt */
#define IEM_I2C4 42 /* I2C4 interrupt */
#define IEM_I2C5 43 /* I2C5 interrupt */
/*#define IEM_RES 44 --- Reserved --- */
/*#define IEM_RES 45 --- Reserved --- */
/*#define IEM_RES 46 --- Reserved --- */
/*#define IEM_RES 47 --- Reserved --- */
