TMS570LC4357: Internal RAM Test Execution

Hi Shivam,

While power-on reset is asserted (low), the oscillator and internal low power oscillator (LPO) are enabled and start-up by default. After power-on reset is released to a high level, the clock detect circuit (CLKDET) begins to monitor the oscillator. If the oscillator is within a valid range, the oscillator becomes the default clock for the device as it exits reset; if the oscillator is not within a valid range, the clock detect selects the internal high-frequency low power oscillator (HF LPO) as the default clock for the device.

Shivam Kakad said:

1. Firstly, where exactly we have to run this test on internal RAM with respect to PLL. Are we supposed to run this before setting up the PLL or after configuring it?

If the OSC in your system is 16MHz, the HCLK is 16MHz too by default. It is ok to run RAM test and program data to FEE before PLL is enabled. I suggest to perform the RAM test, CPU selftest and FEE operation after system is initialized (flash is set up, PLL is enabled and configured, peripherals are enabled, etc). 

Shivam Kakad said:

2. Is there any relation between the STC self test which is not allowed to reset when the RAM test is performed after PLL?

The default value of the CPU LBIST clock prescaler is’ divide-by-1’ (STCCLKDIV register). If PLL is not enabled, the STC execution speed is GCLK=16MHz (assume OSC=16MHz). It is fine to perform STC sleftest before and after PLL is enabled. 

Normally the STC selftest is done before RAM is tested such as PBIST. There is also no problem to do STC selftest after RAM is tested. 

Shivam Kakad said:

3. What could be the better approach to log the test results in EEPROM, if we are expected to perform the RAM test before PLL?

What is size of the test results? Why do you want to do the test and log the results to EEPROM before PLL is enabled? 

Thanks Wang for your response.

Basically the size for test result is 32-bit word, indicating whether the Internal RAM test is passed or failed; However there is not any specific requirement to perform and log the result in EEPROM before PLL, but as we are facing issues mentioned earlier that, when we execute the RAM test after PLL and everything is setup, specifically the STC self test which performs the Reset, is not happening and build is not coming up; That's why we wanted to understand the possible ways to accomplish this.