TMS570LC4357: tms570lc43xx checkPLL1Slip()

Hi Mingxi,

The HALCoGen doesn't generate this function for LC43x device. Dis you use the checkPLL1Slip() function for TMS570LSx devices instead?  

This function will intentionally generate PLL1 slip. After the PLL1 slip, the clock source is witched to crystal clock. But this function restores the PLL1 at the end. 

mingxi liu said:

时钟就不对了

You can use ECLK to check the internal PLL clock, VCLK, etc. Does the system clock become OSC clock?

王工，我增加一个延时就好了（绿色标注的），请问这是为什么啊。

/* Restore the PLL multiplier value */
systemREG1->PLLCTL1 ^= 0x8000U;

/* Enable PLL1 */
systemREG1->CSDISCLR = 0x2U;

/* Wait till PLL1 is enabled */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->CSDIS & 0x2U) != 0U)
{
} /* Wait */

/*lmx add*/
Delay_us(2000);
/*****/

/* Switch back to the initial clock source */
systemREG1->GHVSRC = ghvsrc_bk;

/* Clear PLL slip flag */
systemREG1->GLBSTAT = 0x300U;

Since there is while() to check the status, delay should not be needed. Did you restore the PLL multiplier at the end?

systemREG1->PLLCTL1 = pllctl1_bk;

王工，我的代码如下。我将时钟源由PLL1转到oscillator ，然后再恢复回来。如果不加delay_us,时钟就恢复不到之前的状态了。

uint32 ghvsrc_bk, pllctl1_bk;

/* Back up the the registers GHVSRC and PLLCTRL1 */
ghvsrc_bk = systemREG1->GHVSRC;
pllctl1_bk = systemREG1->PLLCTL1;

/* Switch all clock domains to oscillator */
systemREG1->GHVSRC = 0x00000000U;

/* Disable PLL1 */
systemREG1->CSDISSET = 0x2U;

/* Wait till PLL1 is disabled */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->CSDIS & 0x2U) == 0U)
{
} /* Wait */

/* Enable PLL1 */
systemREG1->CSDISCLR = 0x2U;

/* Wait till PLL1 is enabled */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->CSDIS & 0x2U) != 0U)
{
} /* Wait */

/*lmx add*/
Delay_us(2000);
/*****/

/* Switch back to the initial clock source */
systemREG1->GHVSRC = ghvsrc_bk;

/* Clear PLL slip flag */
systemREG1->GLBSTAT = 0x300U;

/* Clear ESM flag */
esmREG->SR1[0U] = 0x400U;

/* Restore the PLLCTL1 register */
systemREG1->PLLCTL1 = pllctl1_bk;

Hi Mingxi,

Can you clear the PLL slip flag before enabling the PLL, and try again?

The valid bit (PLL, bit 1) in CSVSTA register is not reset after PLL is disabled, clearing PLL slip flag will unlock and clear the valid bot in CSVSTA register.

王工按照您说的， clear the PLL slip flag before enabling the PLL。但是还是不行。

void checkPLL1Slip(void)
{
uint32 ghvsrc_bk, pllctl1_bk;

/* Back up the the registers GHVSRC and PLLCTRL1 */
ghvsrc_bk = systemREG1->GHVSRC;
pllctl1_bk = systemREG1->PLLCTL1;

/* Switch all clock domains to oscillator */
systemREG1->GHVSRC = 0x00000000U;
{

/* Disable PLL1 */
systemREG1->CSDISSET = 0x2U;

/* Wait till PLL1 is disabled */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->CSDIS & 0x2U) == 0U)
{
} /* Wait */

/* Restore the PLL multiplier value */
//systemREG1->PLLCTL1 ^= 0x8000U;

/* Clear PLL slip flag */
systemREG1->GLBSTAT = 0x300U;

/* Enable PLL1 */
systemREG1->CSDISCLR = 0x2U;

/* Wait till PLL1 is enabled */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->CSDIS & 0x2U) != 0U)
{
} /* Wait */

/*lmx add*/
//Delay_us(2000);
/*****/

/* Switch back to the initial clock source */
systemREG1->GHVSRC = ghvsrc_bk;

/* Clear PLL slip flag */
//systemREG1->GLBSTAT = 0x300U;

/* Clear ESM flag */
esmREG->SR1[0U] = 0x400U;

/* Restore the PLLCTL1 register */
systemREG1->PLLCTL1 = pllctl1_bk;
}
}

Hi Mingxi,

I'd like to double check. Do you get PLL slip after systemREG1->PLLCTL1 ^= 0x8000U is called?

What is value of systemREG1->GLBSTAT after systemREG1->PLLCTL1 ^= 0x8000U?

王工

       我把PLL slip注释掉了，也就是我没让pll产生slip。我就是先让pll转到oscillator，然后再恢复pll。但是没有恢复成功。