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TMS570LC4357: Floating Point Overflow and Underflow Detection

James Kiessling
Intellectual 380 points
Part Number: TMS570LC4357


Hello,

Our project uses floating point calculations, the results of which we need to check for overflow and underflow. I've tried including the <fenv.h> library, which I can verify is a part of the compiler's core libraries, but the overflow and underflow exceptions aren't being raised. Turning on the FENV_ACCESS(ON) #pragma doesn't work either and CCS issues a warning that the #pragma is unrecognized.

I'm wondering if there's an interrupt vector that's generated or perhaps some register flags that could be read to detect overflow/underflow?

Additional information if it helps - the compiler used is TI v20.2.0.LTS.

Thank you,

James

  • +1
    Guru 92251 points
    James Kiessling said:
    I'm wondering if there's an interrupt vector that's generated or perhaps some register flags that could be read to detect overflow/underflow?

    There is the Floating-Point Status and Control Register which has the the following flags which indicate if overflow or underflow have occurred, as well as some other floating point "errors":

    [7] IDC Input Subnormal cumulative flag, resets to zero
    [4] IXC Inexact cumulative flag, resets to zero
    [3] UFC Underflow cumulative flag, resets to zero
    [2] OFC Overflow cumulative flag, resets to zero
    [1] DZC Division by Zero cumulative flag, resets to zero
    [0] IOC Invalid Operation cumulative flag, resets to zero

    The c15, Secondary Auxiliary Control Register has the IXC, OFC, UFC, IOC, DZC and IDC bits which can be set to propagate the above floating point "errors" to FPU signals

    Floating point exception handling explains how the FPU signals can be used to generate a VIM interrupt. On a TMS570LC4357 VIM channel 47 is for FPU interrupts.

    I haven't yet tested detection of floating point overflow/underflow but did have an existing project which tested generating a float point division-by-zero setting the DZC flag in the FPSCR. E2E_example_projects/HL_sys_main.c at master · Chester-Gillon/E2E_example_projects · GitHub contains a modification which demonstrates getting an interrupt when a floating point division-by-zero occurs. On the 1st pass no interrupt is enabled, but on the 2nd and subsequent iterations an interrupt is enabled.

    The use of inline assembler statements means the code isn't production-quality, but it might help.

  • 0 in reply to Chester Gillon
    Intellectual 380 points

    Thank you for the reply. The example project was exactly what I needed, I just changed the constants for the overflow and underflow register bits. 

    - James