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RM46L852: How are triggered mibspiHighLevelInterrupt and mibspiLowLevelInterrrupt ?

Fabian Minary
Prodigy 60 points
Part Number: RM46L852

Hello everyone !

I'm using a launchlx2-rm46 board as SPI master and a custom board as SPI slave.

I'm using the standard SPI mode for both and the polling mode for the master and the interrupt mode for the slave.

When I use spiSendAndGetData on the slave to receive and transmit a frame of three bytes I've two mibSpi interrupt gererated (Transmit Buffer Empty Interrupt) just after the call of the function without sending any data from the master,  Is that normal ?

So I'm wondering what does trigger the mibSpi interrupts ?

Best Regards,

Fabian

  • 0
    TI__Guru**** 196206 points
    Fabian Minary said:
    When I use spiSendAndGetData on the slave to receive and transmit a frame of three bytes I've two mibSpi interrupt gererated (Transmit Buffer Empty Interrupt) just after the call of the function without sending any data from the master,  Is that normal ?

    It is correct. The transmit empty interrupt is generated after spiInit() and TX/RX interrupt are enabled since the TXBUFF is empty. The next transmit empty interrupt is generated when a word is copied to the shift register either directly from SPIDAT0/SPIDAT1 or from the TXBUF register.

    Receive complete interrupt is generated when a word is received and copied into the buffer register (SPIBUF).