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AM2732: Clock source (VCLK) selection and frequency for MSS_UARTB

Daisuke Maeda
Guru 20285 points
Part Number: AM2732
Other Parts Discussed in Thread: AWR2944,

The mmWave Demo Visualizer app requires that the baud rate of the COM port for the Auxiliary Data Port be set to the value as 892857 for AM273X.

Our customer wants to use different baud rate for their custom application.

The UART baud rate is the frequency of VCLK divided by an integral multiple of 16 in the UART/SCI module.

MSS_UARTB seems to be used as the Auxiliary Data Port on the TMDS273GPEVM.

In "Table 5-1709. Configuration Options" on the TRM, the MSS_UARTB seems to be selectable from eight clock sources.

0 WUCPUCLK: [What is the WUCPUCLK?]
1 XTALCLK: Input Clock to CLKP/CLKM pins (40/50 MHz)
2 SYS_CLK: It seems to be selectable from eight clock sources
3 DPLL_PER_HSDIV0_CLKOUT1: PER_PLL_HSFIV0_CLKOUT1 (450/480/500 MHz) in "Figure 5-1700. Clock Tree Configuration"
4 DPLL_CORE_HSDIV0_CLKOUT2: CORE_PLL_HSDIV0_CLKOUT2 (400 MHz) in "Figure 5-1700. Clock Tree Configuration"
5 RCCLK10M: [What is the RCCLK10M?]
6 XREF_CLK0: Reference Clock to XREF_CLK0 pin
7 RCCLK10M: [What is the RCCLK10M?]

The clock selected from the eight clock sources seems to be divided. Is this divided clock the VCLK for MSS_UARTB?

In "Table 5-1709. Configuration Options" on the TRM, the SYS_CLK seems to be selectable from eight clock sources.

0 XTALCLK: Input Clock to CLKP/CLKM pins (40/50 MHz)
1 RCCLK10M : [What is the RCCLK10M?]
2 DPLL_CORE_HSDIV0_CLKOUT2: CORE_PLL_HSDIV0_CLKOUT2 (400 MHz) in "Figure 5-1700. Clock Tree Configuration"
3 RCCLK10M: [What is the RCCLK10M?]
4 RCCLK10M: [What is the RCCLK10M?]
5 RCCLK10M: [What is the RCCLK10M?]
6 WUCPUCLK: [What is the WUCPUCLK?]
7 RCCLK10M: [What is the RCCLK10M?]

Can the VCLK for MSS_UARTB be selected from these clock sources?

In in "Figure 5-1700. Clock Tree Configuration", the output clock frequency (e.g. MODE 3 : 450/480/500 MHz) for each PLL and each divider is described.

Should the described frequencies be used for the output clocks of each PLL and each divider?

Best regards,

Daisuke

  • +1
    TI__Expert 8050 points

    Daisuke,

    The selected clock from the sources go through an extra divider before it reaches the peripheral. This divided clock that is the input to the peripheral would be considered the VCLK.

    Also, since SYS_CLK is one of the possible clock sources that you can select for MSS_UARTB from, then the current SYS_CLK configuration will affect MSS_UARTB if SYS_CLK is the source that is being selected in the clock mux.

    As for the values given in Figure 5-1700, ultimately these output values from each PLL and divider will vary based on your ADPLLJ configuration which affects the value of the CLKOUT that feeds into the HS Dividers. The variables that affect the value of CLKOUT can be found under section 5.3.4.2 ADPLLJ Programming Sequence in the TRM

    Hope this helps, please don't hesitate to reach back if you have more questions.

    Best,

    Daniel 

  • 0 in reply to Daniel Bermudez
    Guru 20285 points

    Hi Daniel-san,

    Thank you for your reply.

    I understand that the values given in Figure 5-1700 are typical values and that different values from the values can be used for the output values from each PLL and divider.

    Our customer will change the MSS_UARTB baud rate to the desired value by changing the clock selection and the output clock of each PLL and divider.

    Could you tell me what the WUCPUCLK and the RCCLK10M in "Table 5-1709. Configuration Options" indicate respectively?

    By the way, I posted a similar question for AWR2944 but have not received a clear answer.

    Could you help me regarding my post below?

    e2e.ti.com/.../awr2944-baud-rate-of-com-port-for-the-auxiliary-data-port

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 8050 points

    Hi Daisuke,

    Yes, the values in Figure 5-1700 are typical for Mode 3 operation, which corresponds to the mmWave usecase with lower ADPLL lock frequency.

    WUCPUCLK corresponds to an external XTAL or RC oscillator, the typical values for this are 10/40/50 MHz

    RCCLK10M corresponds to an internal 10 MHz RC oscillator

    As for the other E2E post. Our AM2732 AND AWR2944 devices are based of the same architecture, so everything that was talked about here should still apply to that other device as al the concepts should be backwards compatible. However, I highly suggest to verify with the Radar team just in case there are any specific discrepancies between the two.

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    Guru 20285 points

    Hi Daniel-san,

    Thank you for your reply.

    I understand the following for the VCLK of MSS_UARTB.

    For MSS_UARTB clock (VCLK):

    0 WUCPUCLK: Input Clock to CLKP/CLKM pins or Internal 10 MHz RC oscillator clock (10 MHz/40 MHz/50 MHz)
    1 XTALCLK: Input Clock to CLKP/CLKM pins (40/50 MHz)
    2 SYS_CLK: Selectable from eight clock sources
    3 DPLL_PER_HSDIV0_CLKOUT1: PER_PLL_HSFIV0_CLKOUT1 (450/480/500 MHz)
    4 DPLL_CORE_HSDIV0_CLKOUT2: CORE_PLL_HSDIV0_CLKOUT2 (400 MHz)
    5 RCCLK10M: Internal 10 MHz RC oscillator clock (10 MHz)
    6 XREF_CLK0: Reference Clock to XREF_CLK0 pin
    7 RCCLK10M: Internal 10 MHz RC oscillator clock (10 MHz)

    For SYS_CLK:

    0 XTALCLK: Input Clock to CLKP/CLKM pins (40/50 MHz)
    1 RCCLK10M : Internal 10 MHz RC oscillator clock (10 MHz)
    2 DPLL_CORE_HSDIV0_CLKOUT2: CORE_PLL_HSDIV0_CLKOUT2 (400 MHz)
    3 RCCLK10M: Internal 10 MHz RC oscillator clock (10 MHz)
    4 RCCLK10M: Internal 10 MHz RC oscillator clock (10 MHz)
    5 RCCLK10M: Internal 10 MHz RC oscillator clock (10 MHz)
    6 WUCPUCLK: Input Clock to CLKP/CLKM pins or Internal 10 MHz RC oscillator clock (10 MHz/40 MHz/50 MHz)
    7 RCCLK10M: Internal 10 MHz RC oscillator clock (10 MHz)

    If I have any new questions, I will post them in a new thread.

    Best regards,

    Daisuke