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MCU-PLUS-SDK-AM273X: L3 access word alignment requirement

Adam Yao94020
Genius 10920 points

Part Number: MCU-PLUS-SDK-AM273X

Hi champion,
   My customer found if they access L3 from MSS for a non word (4 byte) aligned address, the MSS jumps to corruption.

for example:

*(uint32_t *)(0x88363660) = 1; ->no problem
*(uint32_t *)(0x88363661) = 1; -> MSS crashes

  While there is no problem for non word aligned access to L2 .

*(uint32_t *)(0x102bcbcd) = 1;->no problem

  May I know what is the reason?

Thanks,
Adam

  • 0
    TI__Mastermind 27743 points

    Hi Adam,

    I am checking with SW team if any known limitation. Will come back on this tomorrow.

    Regards,

    Prasad

  • 0 in reply to Prasad Jondhale
    TI__Mastermind 27743 points

    Adam,

    Follow up queries from our SW expert -

    Is the L3 memory cached or uncached ?

    Unaligned access will trigger exception based on cortex R5 config register setting. If it works for L2 is suspect it is some issue with caching.

    We are also trying to reproduce this issue at our end.

    Regards,

    Prasad

  • 0 in reply to Prasad Jondhale
    TI__Genius 10920 points

    Hi Prasad,
       I am testing the issue in C:\ti\mcu_plus_sdk_am273x_08_01_01_06\examples\drivers\gpio\gpio_led_blink\am273x-evm\r5fss0-0_nortos project. In this project, the MPU setting does not set the L3 MPU, so I guess by default L3 is non cacheable.

    Thanks,
    Adam

  • 0 in reply to Adam Yao94020
    TI__Mastermind 27743 points

    Hi Adam,

    Further update on this based on experiments we did at our end.

    Unaligned access works on memory marked as cached/uncached. It results in exception when memory is marked strongly ordered.

    We confirmed instruction generated is for C code is  *(uint32_t *)(0x88363661) = 0xDEADFACE;

     10276c20:   E3031661            movw       r1, #0x3661

    10276c24:   E3481836            movt       r1, #0x8836

    10276c28:   E5810000            str        r0, [r1]

      

    This confirms str works with unaligned memory and the data is updated corrected in memry starting at location 0x88363661

     We believe, it is expected that unaligned access to strongly ordered memory results in exception . We will follow up with design team to understand why this is the case. 

    Regards,

    Prasad

  • 0 in reply to Prasad Jondhale
    Guru 92251 points
    Prasad Jondhale said:
    We believe, it is expected that unaligned access to strongly ordered memory results in exception . We will follow up with design team to understand why this is the case. 

    The Memory system implications for AXI accesses section in the ARM Cortex-R5 Technical Reference Manual r1p2 contains:

    However, Device and Strongly Ordered memory is always Non-cacheable. Also, any unaligned access to Device or Strongly Ordered memory generates an alignment fault and therefore does not cause any AXI transfer.

    I.e. appears to part of the ARM design rather than anything specific to the AM273x.

  • 0 in reply to Chester Gillon
    TI__Mastermind 27743 points

    Thanks for confirming, Chester. Appreciate your kind inputs.