MCRC Occurrence of Reserved Interrupt Condition

Tony Morrell

Hi,

I am using channel 1 of the MCRC in Semi-CPU Mode at a frequency of 16KHz. I am witnessing an occurrence of a reserved interrupt condition (offset value 0x5) at an approximate frequency of 0.05Hz, that is three of four times every minute.

Please can you give me an indication of what this reserved interrupt condition is. Presumably the set 0x5 to 0x8 are associated with channels 1 to 4, as are 0xd to 0x10 for maybe another reserved interrupt condition.

I would also appreciate advice on what action to take when encountering one of these reserved conditions.

Regards, Tony.

over 14 years ago

0 Haixiao Weng over 14 years ago

TI__Genius 13810 points

I checked the VHDL code. 0x5 is reserved for chan5 CRC fail. And in the VHDL code, since there is no chan5-8, the interrupt vector is tied to zero. 0xd to 0x10 are reserved for chan5-8 compression complete. They are also tied to zero. I do not know why this occurs.

Regards,

Haixiao

0 Brian Fortman over 13 years ago in reply to Haixiao Weng

TI__Expert 7650 points

Tony,

Did you find some other explanation for what you were seeing? Or find a workaround?

0 Tony Morrell over 13 years ago in reply to Brian Fortman

Genius 4130 points

Hi Brian,

I have worked around this problem by just taking no action on the interrupt and have essentially put it on the back burner for the moment. I have just tried it in the lab again and didn't actually witness an occurrence of the problem. Might this be due to using different silicon variants, between TMX570 and TMP570?

Regards, Tony.

0 Haixiao Weng over 13 years ago in reply to Tony Morrell

TI__Genius 13810 points

The silicon on TMX570 and TMP570 should be the same. The test flow is different. I will close this post for now. If you can repeat the problem in the future. Please send the test case to me. Haixiao.weng@ti.com.

Regards,

Haixiao

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MCRC Occurrence of Reserved Interrupt Condition