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TMS570LS3137: Exceed Td(scsl-senal)s DS max value

Part Number: TMS570LS3137


Hi experts,

My customer is testing the time of the SPI Slave Td(scsl-senal)s.

The time of Td(scsl-senal)s is as follows of DS.(CSHOLD = 0, CLOCK PHASE = 0, clock polarity = 0)

The formula for calculating the MAX value is as follows.

tc(VCLK) + tf(ENAn) + 27

The customer parameters are as follows.

Parameter Item Parameter unit
f(vclk) 90 MHz
tc(vclk) 11.11111111 ns
Tc(spc)m
[clock]
66.592 (SPICLK = 15MHz) ns
Tr(spc)m[clock] 2.5 ns
Tf(spc)m[clock] 2.5 ns
Tr(spics)m[cs] 2.5 ns
Tf(spics)m[cs] 2.5 ns
Tr(miso)m[miso] 2.5 ns
Tr(enan)s[ena] 17.40 ns
Tf(enan)s[ena] 3.72 ns
C2Tdelay 8 -
T2Cdelay 8

-

Calculating Td(scsl-senal)s using this parameter the following:

=tc(VCLK) + tf(ENAn) + 27

=11.11ns + 3.72ns + 27

= 41.83ns

However, when the customer measures this waveform on the customer's original board, this value is 87.56ns.

In other words, it exceeds the maximum value of DS.

Do you know why this value exceeds the maximum value for DS?

Best regards,
Sasaki

  • Hi Sasaki-san,

    1. Has the new data been written to the SPI-Slave buffer before SPI-master CS is asserted?

    2. The TRM says that "If C2TDELAY is programmed a non-zero value, then C2EDELAY will start only after the C2TDELAY completes." and SPIENA sample point is between

    (C2TDELAY+1) * tc(VCLK) - tf(SPICS) – 29 and (C2TDELAY+1) * tc(VCLK)