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AM2434: Task Manager is not working

Luca Valenziano
Prodigy 30 points
Part Number: AM2434

Hello,

i want to implement the Task Manager for the PRU0_0 but it is not possible.

I set up all Task Manager register and connectet the Task 2 Subtask 0 to the Host Interrupt 12. After the Interrupt occurs, the TS2_STATE filed in the TASKS_MGR_GLOBAL_STATUS register is set to 1h. But looking at the PRU0 Control Register, the TS_ENABLE field is 0. I tried tsen 1 with the silicon version 4 and also the .word 0x32800000 but no changes at all. I have no idea what the problem could be.

Regards

Luca

  • 0
    TI__Mastermind 27814 points

    Hi
    Can you please share the register dump of PRU_TASKS_MGR_TASKS_MGR_PRU0 Registers (See Table 6-2481 in TRM) - 0x52 starting bytes from address 0x3002A000 or 0x300AA000 (based on the ICSSG instance)?

    And what mode have you selected in "Bit 29-26 PR1_PRU0_GP_MUX_SEL" field of ICSSG_GPCFG0_REG register?

    Regards
    Dhaval Khandla

  • 0 in reply to Dhaval Khandla
    Prodigy 30 points

    Hello,

    here are the registers. I am using the ICSSG 0 - PRU 0. As you can see, the interrupt sets the Bit 4 in 0x3002A004 but the PC does not change to the address 100h configured in Bit 13-0 in 0x3002A01C.

    Bit 29-26 in PR1_PRU0_GP_MUX_SEL is 0h (GP selected). 

    Task_Manager_Register_2.dat

    Data in TI Data file type and 32-Bit Hex - TI Style

    Thanks

    Luca

  • 0 in reply to Luca Valenziano
    TI__Mastermind 27814 points

    Hi
    Sorry for the late response.

    Configured PC address is in code word units. So 0x100 means actual address to configure 0x100/4.

    If you are using assembly, there is a macro $CODE() which you can use. Following is an example :

    m_pru_tm_ts1_pc_set .macro TEMP_REG, TM_BASE, ts1_pc_s0, ts1_pc_s1, ts1_pc_s2, ts1_pc_s3, ts1_pc_s4
    ldi32 TEMP_REG.reg1.x, TM_BASE
    ldi TEMP_REG.reg2.x, $CODE(ts1_pc_s0)
    ldi TEMP_REG.reg3.x, $CODE(ts1_pc_s1)
    ldi TEMP_REG.reg4.x, $CODE(ts1_pc_s2)
    sbbo &TEMP_REG.reg2.x, TEMP_REG.reg1.x, CSL_ICSS_G_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR_TS1_PC_S0, 12
    ldi TEMP_REG.reg2.x, $CODE(ts1_pc_s3)
    ldi TEMP_REG.reg3.x, $CODE(ts1_pc_s4)
    sbbo &TEMP_REG.reg2.x, TEMP_REG.reg1.x, CSL_ICSS_G_PR1_TASKS_MGR_PRU0_PR1_TASKS_MGR_PRU0_MMR_TS1_PC_S3, 8
    .endm

    Regards
    Dhaval Khandla