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TMS570LC4357: How to generate exception/interrupt for floating-point divide by zero.

Tyler Julian
Prodigy 10 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

The ARM technical manual for R5 MCUs says that the divide-by-zero exception mask can be disabled by writing to the DZC bit in the Secondary Auxiliary Control Register. [ 4-26]. 

How do I check that the exception/interrupt is being called? I am using halcogen with version 9.3.0 of CCS.

I have verified that the DZC is set to 1 and that the compiler isn't optimizing the divide by zero away. Here is the code that I am using to the test the feature and a screenshot of the assembly stepping.

volatile float x = 0.0;
volatile float test = 12.2 / x;

  • 0
    TI__Guru**** 198546 points

    Hi Tyler,

    1. The DZC enable needs to be set in the c15 Secondary Auxiliary Control Register in order to let the FPSCR.DZC status flag cause an interrupt request to be generated. The Cortex R4/5 TRM includes example assembly instructions to read from and write to this register:

            MRC   p15,    0,      r0,      c15,  c0,  0 
            ORR   r0,      r0,      #0x000200    
            MCR   p15,    0,      r0,      c15,  c0,  0 

    2. Enable the VIM channel 47 which is mapped to FPU interrupt. In HalCoGen conf GUI, you need to define a ISR for this INT:

    3. Clear bit 19 of CP15 Control register (SCTLR) to disable the generation of Undefined instruction exception

    MRC p15, 0, <Rd>, c1, c0, 0 ; Read SCTLR
    MCR p15, 0, <Rd>, c1, c0, 0 ; Write SCTLR

  • 0
    Guru 92251 points
    Tyler Julian said:
    How do I check that the exception/interrupt is being called?

    To add to what QJ Wang has said, in TMS570LC4357: Floating Point Overflow and Underflow Detection there is a link to an example program.