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FLA11: How to Implement this test?

Max Wittekind
Expert 1895 points

Part Number: TMS570LC4357

Hi experts,

I am currently trying to implent the FLA11 test listed in the safety manual. I started by reading the description in the Technical Reference (chapter 7.7.2.2) and then looked at the implementation in the Safe TI Library.
My Problem now, is that I cannot get it to work and I do not fully understand the values used in the Safe Ti Library.
The following is my understanding of this test:

Testing for 2-Bit-Errors:
1. Branch to non flash region
2. FDIAGCTRL = 0x00050007
3. (From Ti-Library:) FEMU_DMSW = 0x0 and FEMU_DLSW = 0x0
4. (From Ti-Library:) FEMU_ECC  =  0x03
5. Select Port
6. Set DIAG_TRIG to 1
7. Read from flash (Safe TI Library uses Address 0x000000016)
8. Check if ESM 2.3 is set.

(Q1) Why is in step 4 the vector FEMU_ECC = 0x03?
(Q2) Is there a reason why in step 7 the Address is 0x000000016?
(Q3) If I understand this correctly a 2-Bit Error leads to a Data-Abort and ESM 2.3 correct?

Testing for 1-Bit-Errors:
Prerequisites:
    - EPC configuration: SERRENA = Ah
    - 4th bit of PMU PMCR must be 0x1


1. Branch to non flash region
2. FDIAGCTRL = 0x00050007
3. (From Ti-Library:) FEMU_DMSW = 0x0 and FEMU_DLSW = 0x0
4. (From Ti-Library:) FEMU_ECC  =  0xCE
5. Select Port
6. Set DIAG_TRIG to 1
7. Read from flash (Safe TI Library uses Address 0x00000008)
8. Check if ESM 1.4 is set.
9. clear CAM and FIFO in EPC

(Q4) Why is in step 4 the vector FEMU_ECC = 0xCE?
(Q5) Is there a reason why in step 7 the Address is 0x00000008u?
(Q6) If I understand this correctly a 1-Bit Error does not lead to a Data-Abort but to ESM 1.4, correct?

Thank you and best regards,
Max

  • 0
    TI__Guru**** 200256 points
    Max Wittekind said:
    (Q1) Why is in step 4 the vector FEMU_ECC = 0x03?

    This value will XOR the ECC value of flash content at the address you are reading (ox00000016). FEMU_ECC=0x3--> flip first 2 bits of the ECC value to inject 2-bit ECC error.

    FEMU_DMSW = 0x0 and FEMU_DLSW = 0x0 --> XOR with your reading address. DMSW/DLSW=0x0 --> doesn't change the address 

    Max Wittekind said:
    (Q2) Is there a reason why in step 7 the Address is 0x000000016?

    You can use any valid flash address. This address will be XORed with the values in DMSW and DLSW, and its ECC will be XORed with the value in FEMU_ECC

    Max Wittekind said:
    (Q3) If I understand this correctly a 2-Bit Error leads to a Data-Abort and ESM 2.3 correct?

    The uncorrectable ECC error will lead data abort

  • 0
    TI__Guru**** 200256 points
    Max Wittekind said:
    (Q3) If I understand this correctly a 2-Bit Error leads to a Data-Abort and ESM 2.3 correct?

    This test doesn't generate real flash ECC error, so doesn't generate data abort

  • +1 in reply to QJ Wang
    TI__Guru**** 200256 points

    Hi Max,

    Max Wittekind said:
    (Q4) Why is in step 4 the vector FEMU_ECC = 0xCE?

    0xCE is the syndrome from the Syndrome Table. From the syndrome table, 0xCE means a single bit error in data bit 0. 

    Max Wittekind said:
    (Q5) Is there a reason why in step 7 the Address is 0x00000008u?

    Any valid flash address would be fine.

    Max Wittekind said:
    (Q6) If I understand this correctly a 1-Bit Error does not lead to a Data-Abort but to ESM 1.4, correct?

    ESM 1.4 is EPC error. EPC performs error profiling on the correctable fault (flash, SRAM, eeprom) and trigger serr_event to ESM if the address of the
    correctable fault is not part of the CAM.