EK-TM4C1294XL: SysCtlDelay is giving me a 1.5ms delay when I am (I think) asking for 1ms, fixed when I enable PLL?

Hello all,

I've been trying to figure out exactly what is going on with my firmware and can't get to the bottom of it... I am using the EK-TM4C1294XL dev board with the 25MHz xtal as the main osc.

I have got a simple delay running in a loop and I am probing the output on a scope, here is my code:

    /*DOES NOT WORK (1.5ms)*/
    clockFreqency = SysCtlClockFreqSet(SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_25MHZ, 25000000);
    /*WORKS (1.02ms)*/
    clockFreqency = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 25000000);
    //assert(clockFreqency == 25000000);

    /*test pin init*/
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    GPIOPinTypeGPIOOutput(GPIOC_AHB_BASE, GPIO_PIN_4);

    while(1){
        GPIOPinWrite(GPIOC_AHB_BASE,GPIO_PIN_4, GPIO_PIN_4);
        uint32_t count = clockFreqency/1000U/3U;
        //3 cycles (0.12us) * 8333 = ~1ms
        SysCtlDelay(count);
        GPIOPinWrite(GPIOC_AHB_BASE,GPIO_PIN_4, 0);
        SysCtlDelay(count);
    }

note: this runs inside of a initialization() function which is called in main once.

With the PLL disabled (as per the first SysCtlClockFreqSet), the function returns 25MHz as its best match I get the following 1.5ms pulse on the GPIO output:

With PLL enabled and the function returning 24MHz as its best match I get ~1ms:

What would be causing this behaviour? Any help is appreciated!

Cameron