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TMS570LC4357: MSP16: How to Test SPI ECC?

Max Wittekind
Expert 1875 points
Part Number: TMS570LC4357


Hi experts,

Neither the Safety manual nor the Technical Reference manual gives detailed instructions on how to test the ECC Logic of the SPI RAM. The SafeTi Lib does not even mention this test.
As far as I can tell, this the way to do the test:

For MibSPI1:
1.Write some value to tx-buffer 1 (Adress = 0xFF0E 0000h)
2. Turn on Testmode ( 0x1 to EDAC_MODE)
3. Flip 1 ECC bit (single-bit error) at Adress 0xFF0E 0000 + 0x400h (normal mode)
4. Disable testmode ( 0x0 to EDAC_MODE)
5 Read from Adress 0xFF0E 0000h
6. Check ESM 1.77 and PAR_ECC_STATT Register for single-bit error
7. Turn on Testmode ( 0x1 to EDAC_MODE)
8. Flip bit again to correct failure
9. Disable testmode ( 0x0 to EDAC_MODE)

11....Do the same for double-bit error, but flip two ECC-Bits and check esm 1.17

(Q1) Is this the correct way to test the ECC Mechanism?

Thank you and best regards,
Max

  • 0
    TI__Mastermind 29778 points

    Hi, our expert is out of office until 4/7. Please expect a delayed response.

    Also, please see this FAQ: software-dl.ti.com/.../index.html

  • 0 in reply to Frank Livingston
    TI__Guru**** 198766 points

    Hi Max,

    You can use the SDL API: sl_selftest_mibpsi()

    1. Enable ECC memory test enable: bit 8 of PAR_ECC_CTRL register

    2. Enable RXRAM access: bit 16 of MIBSPIE register

    3. Enable ECC diag mode: bit[3:0] of ECCDIAG_CTRL register, to enable write/read to/from ECC space

    4. Enable single bit error event: bit[27:24], SBE_EVT_EN of PAR_ECC_CTRL register, to enable the error generation whenever a 1-bit error is detected.

    5. Flip 1-bit or 2-bit of data in one location of MibSPI RAM, or ECC value 

    6. Enable SECCED: bit[3:0], EDEN of PAR_ECC_CTRL register, to enable ECC error detection

    7. Read data 

  • 0 in reply to QJ Wang
    Expert 1875 points

    Hi QJ,

    We enable the Single bit error event (SBE_EVT_EN) and the SECCED (PAR_ECC_CTRL) when we initialize SPI.

    This would mean that step 4 and 6 can be skipped. Correct?

    Thank you and best regards,
    Max

  • 0 in reply to Max Wittekind
    TI__Guru**** 198766 points

    Hi Max,

    I will double check it, then come back to tomorrow morning.

  • 0 in reply to QJ Wang
    TI__Guru**** 198766 points
    Max Wittekind said:
    This would mean that step 4 and 6 can be skipped. Correct?

    1. For 1-bit ECC test, SBE_EVT_EN should be disabled, otherwise the data is corrected whenever you flip the bit of the data (step 5).

    2. The EDEN (PAR_ECC_CTRL) should be enabled in mibspiInit() to ensure the ECC is programmed correctly when mibspiInit() program status bits to TX RAM and RX RAM. 

    3. The EDEN (PAR_ECC_CTRL) needs to be disabled before flipping the bit otherwise the ECC will be updated

  • 0 in reply to QJ Wang
    TI__Guru**** 198766 points

    /** Initialize MIBSPI */
    mibspiInit();   --> the SECCED should be enabled (EDEN=0xA of PAR_ECC_CTRL register)

    //1. Enable ECC memory test enable: bit 8 of PAR_ECC_CTRL register
    mibspiREG1->PAR_ECC_CTRL = 0x0A050105; -->SECCED is disabled, and Enable the error signaling

    //2. Enable RXRAM access: bit 16 of MIBSPIE register
    //mibspiREG1->MIBSPIE |= 1<<16;   -->don't need if you only test TX RAM

    //3. Enable ECC diag mode: bit[3:0] of ECCDIAG_CTRL register, to enable write/read to/from ECC space
    mibspiREG1->ECCDIAG_CTRL = 0x5; //enable ECC write   -->don't need if you don't change ECC bit

    //4. Enable single bit error event: bit[27:24], SBE_EVT_EN of PAR_ECC_CTRL register, to enable the error generation whenever a 1-bit error is detected.
    mibspiREG1->PAR_ECC_CTRL |= 0x5 << 24;  -->Disable the 1-bit ECC error correction, don't need this step if it is disabled in step 1

    //5. Flip 1-bit or 2-bit of data in one location of MibSPI RAM, or ECC value

    //*(unsigned int*)(0xff0e0404) ^= 0x01;  --> flip 1-bit of ECC value

    *(unsigned int*)(0xff0e0004) ^= 0x01;  --> flip one bit of data 

    //6. Enable SECCED: bit[3:0], EDEN of PAR_ECC_CTRL register, to enable ECC error detection

    mibspiREG1->PAR_ECC_CTRL = 0x0A05010A;  -->Enable SECCED

    unsigned int value = *((volatile uint32 *)0xFF0E0004U);

    *(unsigned int*)(0xff0e0004) = backup;

    Hope this is helpful.

  • 0 in reply to QJ Wang
    Expert 1875 points

    Hi QJ,

    this helps a lot. But I have a question about the function of the SBE_EVT_EN bit. I thought this would enable the signaling that a single bit error has occured and not the correction.

    That is why I thought this need to be enabled for the 1-Bit error Test?

  • +1 in reply to Max Wittekind
    TI__Guru**** 198766 points

    You are correct. The SBE_EVT_EN should be enabled, but the EDAC_MODE should be disabled.

    /** Initialize MIBSPI */
    mibspiInit();   --> the SECCED should be enabled (EDEN=0xA of PAR_ECC_CTRL register)

    //1. Enable ECC memory test enable: bit 8 of PAR_ECC_CTRL register
    mibspiREG1->PAR_ECC_CTRL = 0x0A050105; -->SECCED is disabled, and Enable the error signaling

    //2. Enable RXRAM access: bit 16 of MIBSPIE register
    //mibspiREG1->MIBSPIE |= 1<<16;   -->don't need if you only test TX RAM

    //3. Enable ECC diag mode: bit[3:0] of ECCDIAG_CTRL register, to enable write/read to/from ECC space
    mibspiREG1->ECCDIAG_CTRL = 0x5; //enable ECC write   -->don't need if you don't change ECC bit

    //4. Enable single bit error event: bit[27:24], SBE_EVT_EN of PAR_ECC_CTRL register, to enable the error generation whenever a 1-bit error is detected.
    mibspiREG1->PAR_ECC_CTRL |= 0xA << 24; -->Enable the single bit error event

    //5. Disable the correction of SBE detected by the SECDED

    mibspiREG1->PAR_ECC_CTRL |= 0x5 << 16;  -->Disable the 1-bit ECC error correction, don't need this step if it is disabled in step 1

    //6. Flip 1-bit or 2-bit of data in one location of MibSPI RAM, or ECC value

    //*(unsigned int*)(0xff0e0404) ^= 0x01;  --> flip 1-bit of ECC value

    *(unsigned int*)(0xff0e0004) ^= 0x01;  --> flip one bit of data 

    //7. Enable SECCED: bit[3:0], EDEN of PAR_ECC_CTRL register, to enable ECC error detection

    mibspiREG1->PAR_ECC_CTRL = 0x0A05010A;  -->Enable SECCED

    unsigned int value = *((volatile uint32 *)0xFF0E0004U);

    *(unsigned int*)(0xff0e0004) = backup;