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AM2432: GPMC-related Clock Questions

Mari Tsunoda
Expert 5726 points
Part Number: AM2432

Hi Team,

One of my customers has a few questions about GPMC-related clock. I've pasted their questions as below:

  1. Could you show timing constraints between GPMC_FCLK_MUX and other GPMC_* signals? On the datasheet, timing constraints between GPMC_FCLK and other GPMC_* signals are shown.
    We have to use GPMC_FCLK_MUX because the slave device needs continuous bus clock. So We need timing constraints on GPMC_CLK_FMUX.
  2. It seems that peripheral blocks need both *_FCLK and *_ICLK. (for example p7326 Figure 12-1589. GPMC Integration)
    There is a little information on *_ICLK signal. We know only 1)it is described as Interface clock, 2)it is generated from MAIN_SYSCLK0 of PLL_CTRL0 and divided by 2.
    What should we do about setting *_ICLK from software? (frequency setting? which divider block should we use?)
  3. Are the signals named GPMC_* and signals named GPMC0_* are identical? In both the datasheet and the TRM, Two notations are mixed.
  4. About the clock source selection of GPMC_FCLK. it is mentioned on Table 5-613(page 2418) and Figure 12-1589(page7326). but it seems that Table5-613 and Figure12-1589 say different information.

Best regards,

Mari Tsunoda

  • +1
    TI__Expert 7630 points

    Hi Mari,

    1. The timing constraints between GPMC_FCLK_MUX and the other GPMC_ * signals should still follow the same characteristics as the ones between GPMC_FLCK and other signals. Note that when using the continuous clock option with synchronous interface options the user should ensure that the GPMC outputs are timed to the same frequency.

    This information can be found in section 12.3.3.4.2 GPMC Clock Configuration of the TRM

    2. There are no peripheral level divider blocks for GPMC_ICLK. this clock is directly derived from MAIN_SYSCLK0 divided by 2 and fed into the system. If you want to modify the frequency of GPMC_ICLK then you would have to directly modify MAIN_SYSCLK0

    3. Yes they are the same signals being referenced.

    4. What is shown on Table 5-613 is a typo. I confirmed the correct clock sources are actually the ones shown in Figure 12-1589 (MAIN_PLL0_HSDIV3_CLKOUT and MAIN_PLL2_HSDIV7_CLKOUT). Please assume that MAIN_PLL2_HSDIV7_CLKOUT is the correct selection when setting the CLK_SEL to 1h.

    Hope this information helps!

    Best,

    Daniel

    Link to TRM: www.ti.com/.../spruim2

  • 0 in reply to Daniel Bermudez
    TI__Expert 5726 points

    Thank you! Will let my customer know.

  • 0 in reply to Mari Tsunoda
    TI__Expert 5726 points

    Hi Daniel,

    We received a follow-up question from our customer from our meeting yesterday regarding 2).

    Daniel Bermudez said:
    The timing constraints between GPMC_FCLK_MUX and the other GPMC_ * signals should still follow the same characteristics as the ones between GPMC_FLCK and other signals

    If the timing constraits between GPMC_FCLK and other GPMC_* signals follow the same characteristics, then wouldn't GPMC0_ICLK be the same as GPMC0_FCLK?

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Expert 7630 points

    Hi Mari,

    ICLK and FCLK don't have to be same since they perform different functions at a peripheral level.

    The ICLK is used by the core to interface with the peripherals (i.e register writes) while the FCLK is used for carrying out the timing functions of the peripherals (i.e. communication protocols and data transfers). This is why the ICLK runs directly into the system after the /2 block, while the FCLK has extra steps of configuration that would ensure the user is setting the clock according to memory timing constraints/requirements.

    Best,

    Daniel