• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 31 subscribers
  • Views 196 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM44L520: Issue using MIBSPI1nCS[3] as GIO

Andrew Mercer
Prodigy 170 points
Part Number: RM44L520
Other Parts Discussed in Thread: HALCOGEN

Hello, 

I am currently trying to use two of the MSBSPI pins as GIO on the RM44L520. I followed the technical manual and was able to get the MIBSPI1nCS[3] pin working by configuring it as GIO in halcogen, call the mibspiInit() initialization function, and using the gioSetPort function to set the mibspiPORT1 register high. I tried following a similar process to configure MIBSPI1nENA for use as GIO but I am not sure which register I should be passing into the gioSetPort function to set this pin. I have tried using the N3HET pin that is assigned to the same pin on this board but it doesn't seem to be working either. I have two main questions: first, where I am changing the MIBSPI1nENA output value using the gioSetPort function are there other pins that are going high that I am not aware of, and if so, is there another register I can set to target that specific pin. Secondly, is there some extra step I am missing to configure the MIBSPI1nCS[3] pin for use as GIO? I am using the 100pin variant of this processor.

Thanks for the help in advance 

  • 0
    TI__Mastermind 29338 points

    Hi, our expert is out of office until 4/7. Please expect a delayed response.
    Also, please see this FAQ: software-dl.ti.com/.../index.html

  • +1
    Prodigy 170 points

    I figured out the issue. Halcogen seems to only have a FreeRTOS project version for the 144pin variant of the RM44L520. As I selected this processor when creating the project, I was unable to configure each pin properly in the multiplexing menu. After switching to the proper, non FreeRTOS version of processor I am using I was able to switch to operation mode of pin 68 to N2Het allowing for it to be used as IO easily. I did find a bug in Halcogen where pin 39 is not included in the multiplexing menu, so I had to add configure that manually. This post below shows the registers that were set to change pin 39's operation mode:

    e2e.ti.com/.../tms570lc0914-pz100-pin-39