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AM2432: GPMC Software Support

Paul Hanson
Prodigy 195 points

Part Number: AM2432

I do not find any source code for the General-Purpose Memory Controller in the SDK (mcu_plus_sdk_am243x_08_02_00_31). We are connecting an FPGA to the GPMC, and we are hoping TI has source code available for setting up the GPMC.

Thanks,

Paul

  • 0
    TI__Guru 57145 points

    Hi Paul,

    Currently the there is no GPMC driver in MCU+ SDK. We will support the GPMC driver in next MCU+ SDK release (8.3.0, by the end of May 2022).

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Prodigy 195 points

    Ming,

    We are connecting two FPGAs to the GPMC. The Technical Reference Manual shows the Configuration register 7 as being at offset 0x78 + formula. Is formula for the different chip selects? Given our two chip selects, what are the values for formula?

    The description of the BASEADDRESS field of the GPMC_CONFIG7_i register states the following:

    CSi base address where i = 0 to 3 (16-MB minimum granularity) bits
    [5-0] corresponds to A29, A28, A27, A26, A25, and A24. See .

    Is the i above for the different chip selects? When it says "See ." what is it referring to? Where do I get more information on how to set up the addressing for the two FPGAs?

    If incomplete source code is available, it would be helpful.

    Thanks,

    Paul

  • 0 in reply to Paul Hanson
    TI__Mastermind 33493 points

    Hey Paul,

    I am looking into your query now and will reach out to our GPMC expert for additional information.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Mastermind 30571 points

    Hi Paul,

    Below is an example of the MASKADDR and BASEADDR for 4 GPMC chip selects (each 16MB).

    BASEADDR[5:0] correspond to the bits 29:24 of the system address. Each GPMC chip select's registers checks the system address to see if it falls within its range by checking against its BASEADDR and MASKADDR. If the system address lies within the range, then that GPMC chip select is accessed (read/write) and the signal timings for that chip select are used.

    There must be no overlap of the chip selects addr range or GPMC will have an address error.

    Yes, the i in the CSi stands for CS0 through CS7. Note AM64 only pins out GPMC0_CS0 through CS3.

    Where the TRM says "See ." in Table 12-3462. GPMC_CONFIG7_i Register Field Descriptions, I believe it was intending to link to 12.3.3.4.7.1 Chip-Select Base Address and Region Size. I'll confirm and file a LitBug against the TRM to fix that broken link. Thanks.

    Hope this helps,
    Mark