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AM2432: Clock Loopback

Mari Tsunoda
Expert 5726 points
Part Number: AM2432
Other Parts Discussed in Thread: SYSCONFIG

Hi Team,

In the context of this E2E thread below, I am creating another thread focused on loopback signals.

Link to E2E Thread

  1. Regarding GPMC_CLKLB and MMC1_CLKLB in SysConfig settings, if the customer were to not tick the box for these signals (as they do not have an associated ball), what would happen? I am assuming that they need to connect the pin, even though there is no ball associated, so is there any documentation that shows what this loopback signals are connected to and what it does? The documentation linked in the previous thread was OSPI/QSPI related, not GPMC/MMC1 related.

Best regards,

Mari Tsunoda

  • 0
    TI__Expert 5726 points

    Hi any update on this?

  • 0 in reply to Mari Tsunoda
    TI__Mastermind 22893 points

    Hey Mari,

    Re-assigning this thread now to get you in touch with the correct expert.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 5726 points

    Hi Zackary,

    Thanks, if possible I would like a response by noon tomorrow Japan time because we have another meeting with them. Sorry for the rush once again.

    Best regards,

    Mari

  • 0
    TI__Mastermind 30110 points

    Hi Mari,

    In the online SysConfig version 1.12.0+2406 ( dev.ti.com/sysconfig)...

    When the checkbox on the left is checked, the output files include the below section that configures PADCONFIG32 to...
    1) select GPMC0_CLKLB muxmode 0 (GPMC0_CLKLB)
    2) set Input enable for the pad (RXACTIVE = 1)
    The RX checkbox on the right is greyed out and always checked (RXACTIVE = 1)
    3) TX_DIS bit remains unwritten and in its default state

    On AM64x, the default state of PADCONFIG32 (GPMC0_CLKLB) has muxmode = 7 (unassigned), RXACTIVE = 0, TX_DIS = 1

    This means that TX_DIS remains 1 (Driver is disabled). This will prevent GPMC_CLKLB from working as a pad-loopback clock. To operate, it needs both Receiver enabled (RXACTIVE = 1) and Driver enabled (TX_DIS = 0).

    For CLKLB to work, I think the the below snippet of output code from SYSCONFIG needs to be modified...

    From:
    /* MyGPMC1 -> GPMC0_CLKLB -> GPMC0_CLKLB */
        {
            PIN_GPMC0_CLKLB, PIN_MODE(0) | \
            ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
        },
        
    To:
    /* MyGPMC1 -> GPMC0_CLKLB -> GPMC0_CLKLB */
        {
            PIN_GPMC0_CLKLB, PIN_MODE(0) | \
            ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION) & (~PIN_OUTPUT_DISABLE))
        },


    If the checkbox on the left is not checked at all, then the output code from SYSCONFIG does not write anything to PADCONFIG32 (GPMC0_CLKLB), leaving it in its default state.
    Again, the default state of PADCONFIG32 (GPMC0_CLKLB) has muxmode = 7, RXACTIVE = 0, TX_DIS = 1. This will not work as a loopback clock.

    Refer to TRM Table 5-105. PADMMR_PADCONFIG32 Register Field Descriptions. Specifically, SPRUIM2C – MAY 2020 – REVISED SEPTEMBER 2021 shows the bit field RESET state leaves TX_DIS = 1, preventing the output buffer from driving the GPMC0_CLK.

    Regards,
    Mark