TMS570LS1114: Why can't RTI interrupts occur periodically？

zhang xiaohong

Part Number: TMS570LS1114

hi，When count0 is set to 1ms, an interrupt will be generated. Only the first interrupt will be generated, not periodic interrupt will be generated. The interrupt flag of RTI is also cleared

Thanks a lot.

over 3 years ago

+1 QJ Wang over 3 years ago

TI__Guru**** 196176 points

Hi Xiaohong,

zhang xiaohong said:
When count0 is set to 1ms

Do you RTI compare 0 like the selection in the pic below, and compare 0 uses counter0?

Please check your RTI config if both compare 0 value and update compare 0 value are set correctly:

rtiREG1->CMP[0U].COMPx and rtiREG1->CMP[0U].UDCPx

+1 QJ Wang over 3 years ago in reply to QJ Wang

TI__Guru**** 196176 points

To allow periodic interrupts, a certain value can be added to the compare value in RTICOMPx automatically. This value is stored in the update compare register (RTIUDCPx) and will be added after a compare is matched.

If RTIUDCPx = 0, only 1 interrupt is generated.

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TMS570LS1114: Why can't RTI interrupts occur periodically？