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MCU-PLUS-SDK-AM243X: PRU Spinlock example needed

Part Number: MCU-PLUS-SDK-AM243X

Hi,

I'm looking for a simple PRU Spinlock example along the lines of the ipc_spinlock_sharedmem_am243x-lp_system_freertos_nortos example. Is one available? Or can a PRU assembler snippet be provided?

What I'm trying to do is have a small (say 256 byte) section of shared memory that is updated by the PRU (which reads from an external peripheral) which is then read and processed by an R5F core.

I'm imagining an RTOS thread on the R5F core waiting on the spinlock. Update rate is 40kHz (or higher if it can be made to work). 

Thanks, Steve

  • Hi Steve,

    I'm looking for a simple PRU Spinlock example along the lines of the ipc_spinlock_sharedmem_am243x-lp_system_freertos_nortos example. Is one available

    No, there aren't any examples of the PRU using the Spinlock hardware. I checked AM64x & AM243x MCU+SDK 08_02_00_31 and the PSSP.

    Using the Spinlock hardware appears simple, judging from the AM64x/AM243x TRM and the AM243x MCU+SDK driver. All that's required is to read or write the MMR for the desired lock.

    The following code snippet from the MCU+SDK driver file mcu_plus_sdk_am243x_08_02_00_31\source\drivers\spinlock\v0\spinlock.c shows the lock and unlock functions:

                int32_t Spinlock_lock(uint32_t baseAddr, uint32_t lockNumber)
                {
                    int32_t         lockStatus = SystemP_FAILURE;
                    CSL_spinlockRegs *pSpinlockRegs = (CSL_spinlockRegs *)((uintptr_t)baseAddr);
    
                    if(lockNumber < Spinlock_getNumLocks(baseAddr))
                    {
                        lockStatus = CSL_REG32_RD(&pSpinlockRegs->LOCK_REG[lockNumber]);
                    }
    
                    return (lockStatus);
                }
    
                void Spinlock_unlock(uint32_t baseAddr, uint32_t lockNumber)
                {
                    CSL_spinlockRegs *pSpinlockRegs = (CSL_spinlockRegs *)((uintptr_t)baseAddr);
    
                    if(lockNumber < Spinlock_getNumLocks(baseAddr))
                    {
                        CSL_REG32_WR(&pSpinlockRegs->LOCK_REG[lockNumber], CSL_SPINLOCK_LOCK_REG_TAKEN_FREE);
                    }
    
                    return;
                }
    

    The PRU cores have access to all SOC resources, so a PRU core can to read/write the Spinlock registers in the same way.

    This is not a complete example, but the following code PRU assembly snippet will read SPINLOCK_LOCK_REG_0:

                LDI32   r0, 0x2A000800
                LBBO    &r1, r0, 0, 4
    

    Something similar should work for writing the Spinlock.

    I'm looping in Nick in case he knows more about this topic.

    Regards,
    Frank

  • Nothing additional to add, Frank got it right.

    For future readers, there are also spinlocks within the AM64x & AM24x PRU_ICSSG. See the TRM for more details.

    Regards,

    Nick