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AM263x cc EVM SBL

carmel gorali
Prodigy 50 points

Hi!

I want to work with FSI1 in SPI mode with 50MHz.

Looking at register CONTROLSS_CTRL_FSI_TX1_CLK_GATE and  CONTROLSS_CTRL_FSI_RX1_CLK_GATE , in AM263xPTRM_RegistersAddendum.pdf (page 663), I can assume that these registers

select the "PLLRAWCLK" in diagram 7-221 page 572 in SPRUJ17_PUBLIC_AM263xTRM.pdf

What is the possible values that these FSI clock gate register can get?

Carmel

  • +1
    TI__Mastermind 22943 points

    Hello Carmel,

    FSI1 at 50MHz in SPI-Compatibility mode is a valid use case.

    1) The CONTROLSS_*_CLK_GATE registers are actually Clock Gates, meaning if the register is set to 0b111, the SYSCLK clock will be blocked and the IP will go "limp" and cease all operations. This functionality can be used to save power when a given IP remains unused. There is also a CONTROLSS_*_PLL_CLK_GATE register that would allow the IP itself to continue to execute, but it would prevent the Transmit Clock Generator from creating a valid TXCLK signal.

    2) You can use the TX_OPER_CTRL_LO.SEL_PLLCLK (pg. 1431 of Register Addendum) to choose between PLLRAWCLK or SYSCLK as the driving clock source for the Transmit Clock Generator.

    SYSCLK is major 200MHz clock that also drives the IP itself.

    PLLRAWCLK is an auxillary (400MHz default) clock with the following source options via the  MSS_RCM_CONTROLSS_PLL_CLK_SRC_SEL Register (pg. 357 of Register Addendum.

    CONTROLSS_PLL_CLK_GCM_CLKSRC_SEL 0 XTALCLK
    1 EXT_REFCLK
    2 DPLL_CORE_HSDIV0_CLKOUT2
    3 DPLL_PER_HSDIV0_CLKOUT1
    4 DPLL_CORE_HSDIV0_CLKOUT0
    5 RCCLK10M
    6 XTALCLK
    7 RCCLK10M

    Best Regards,

    Zackary Fleenor