• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 303 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2634-Q1: Clock in/out

Bernhard Feuerer
Prodigy 105 points
Other Parts Discussed in Thread: AM2634

Hello,
I need additional information about the AM2634 Q1 / SPRSP74 - MARCH 2022.

In the datasheet CLKOUT0 (Ball M2) and CLKOUT1 (Ball B16) are mentioned.
I would like to feed these CLKOUTx into an external FPGA. Ideally, the AM2634 and the FPGA would have a syncronized clock.

Where can I find the characteristics of these CLKOUTx pins?
How much capacitance and mA can these pins drive?


I plan to use a 25MMz or 50MHz oscillator on EXT_REFCLK0 (Ball P2).
Is it possible to drive the AM2364 with a 50MHz clock, or do I need to use 25MHz?

What can I expect in terms of jitter at CLKOUT0 and CLKOUT1 if the clock is derived from EXT_REFCLK0 / 50MHz or 25MHz / 100ppm?

br,
Bernhard

  • 0
    TI__Expert 8050 points

    Hi Bernhard,

    I am working on getting the best support to answer your question. Please expect an update on this thread by Monday 25th. I appreciate your patience on this.

    Best,

    Daniel

  • 0
    TI__Intellectual 1135 points

    Hi Bernhard,

    1. The IO drive current is a function of VOL/VOH that can be tolerated. As an example, at  6ma,  VOH = supply - 0.45   and VOL = 0.45. At lower current the VOH/VOL is better than this. So as a first approximation you can assume a 6 ma drive current.

    2.  The capacitance that can be driven depends on the slew rate that can be tolerated. Higher is the cap , slower is the transition. The IO's supports two slew rate setting (Fast SC1 = 0  and slow SC1 = 1) . As an example, at 5pf load, SC1  = 0 gives a rise time of ~2.2ns and SC1 = 1 gives a rise time of ~2.7ns 

    3. EXT_REFCLK can be driven to 50Mhz. The design is closed upto 100Mhz

    4. The CLKOUT0 and CLKOUT1 cannot be derived from EXT_REFCLK0 in AM263. Only internal clock sources were provisioned to drive CLKOUT*. Here are the sources which can be brought out on the CLKOUT pins.

    0 XTALCLK
    1 DPLL_CORE_HSDIV0_CLKOUT0
    2 DPLL_CORE_HSDIV0_CLKOUT1
    3 DPLL_PER_HSDIV0_CLKOUT0
    4 DPLL_PER_HSDIV0_CLKOUT1
    5 RCCLK10M
    6 RCCLK32K
    7 CTPS_GENF0

    Regards

    Prithvi