• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 449 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM57L843: Stack size in SafeTI Diagnostic Library 2.4.0

Koichiro Tashiro
Mastermind 22935 points
Part Number: RM57L843
Other Parts Discussed in Thread: HALCOGEN

Hi,

My customer uses RM57Lx and SafeTI Diagnostic library.
In the linker command file: 
\SafeTI Diagnostic Library\2.4.0\build\RM57L843_NoOS\SL_RM57L843_NoOS_sys_link.cmd
It seems stack sizes are configured as 2048 bytes each.

    .STACK_DATA_svc     : {. += 2048;} > STACKS, RUN_START(StackModeSVC)
    .STACK_DATA_fiq     : {. += 2048;} > STACKS, RUN_START(StackModeFIQ)
    .STACK_DATA_irq     : {. += 2048;} > STACKS, RUN_START(StackModeIRQ)
    .STACK_DATA_abt     : {. += 2048;} > STACKS, RUN_START(StackModeABT)
    .STACK_DATA_und     : {. += 2048;} > STACKS, RUN_START(StackModeUND)
    .STACK_DATA_sys     : {. += 2048;} > STACKS, RUN_START(StackModeSYS)


On the other hand, the header file:
\SafeTI Diagnostic Library\2.4.0\safety_library\include\sl_config.h
It seems stack sizes are 1024 bytes each.
#define STACK_SIZE_MODE_SVC 1024u   /**< Stack size for SVC mode */
#define STACK_SIZE_MODE_FIQ 1024u   /**< Stack size for FIQ mode */
#define STACK_SIZE_MODE_IRQ 1024u   /**< Stack size for IRQ mode */
#define STACK_SIZE_MODE_ABT 1024u   /**< Stack size for ABT mode */
#define STACK_SIZE_MODE_UND 1024u   /**< Stack size for UND mode */
#define STACK_SIZE_MODE_SYS 1024u   /**< Stack size for SYS mode */


Is this problematic? If so, which one should be modified?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru**** 196816 points

    Hi Koichiro-san,

    It is a SW bug. They should be 2048. The correct one should be:

    #define STACK_SIZE_MODE_SVC 2048u /**< Stack size for SVC mode */
    #define STACK_SIZE_MODE_FIQ  2048u /**< Stack size for FIQ mode */
    #define STACK_SIZE_MODE_IRQ  2048u /**< Stack size for IRQ mode */
    #define STACK_SIZE_MODE_ABT  2048u /**< Stack size for ABT mode */
    #define STACK_SIZE_MODE_UND  2048u /**< Stack size for UND mode */
    #define STACK_SIZE_MODE_SYS  2048u /**< Stack size for SYS mod*/

  • 0 in reply to QJ Wang
    TI__Mastermind 22935 points

    Hi QJ,

    I see. The customer will fix these in sl_config.h.
    BTW, what happens if the bug is not fixed?

    Thanks and regards,
    Koichiro Tashiro 

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 22935 points

    Hi QJ,

    Customer has additional question for stack configuration.
    As we discussed, Safety Library configures SVC, FIQ, IRQ, ABT, UND and SYS. Total 6 stacks.
    On the other hand, HalCoGen does not have SYS stack, but it has USR stack. Total 6 stacks.
    According to ARM R5 TRM, there are 7 operation modes, USR, SVC, FIQ, IRQ, ABT, UND and SYS. Total 7.

    What is correct configuration to use RM57L?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 22935 points

    Hi QJ,

    Customer also found the *.map file does not correspond to what configured in *.cmd file.
    The .STACK_DATA_xxx order defined in *.cmd file is below.
    svc => fiq => irq => abt => und => sys

    *.cmd file 

        .STACK_DATA_svc     : {. += 2048;} > STACKS, RUN_START(StackModeSVC)
    .STACK_DATA_fiq     : {. += 2048;} > STACKS, RUN_START(StackModeFIQ)
    .STACK_DATA_irq     : {. += 2048;} > STACKS, RUN_START(StackModeIRQ)
    .STACK_DATA_abt     : {. += 2048;} > STACKS, RUN_START(StackModeABT)
    .STACK_DATA_und     : {. += 2048;} > STACKS, RUN_START(StackModeUND)
    .STACK_DATA_sys     : {. += 2048;} > STACKS, RUN_START(StackModeSYS)


    But the *.map file shows below order.
    abt =>  fiq => irq => svc => sys => und

    *.map file
    .STACK_DATA_abt
*          0    08020000    00000800     UNINITIALIZED
                  08020000    00000800     --HOLE--

.STACK_DATA_fiq
*          0    08020800    00000800     UNINITIALIZED
                  08020800    00000800     --HOLE--

.STACK_DATA_irq
*          0    08021000    00000800     UNINITIALIZED
                  08021000    00000800     --HOLE--

.STACK_DATA_svc
*          0    08021800    00000800     UNINITIALIZED
                  08021800    00000800     --HOLE--

.STACK_DATA_sys
*          0    08022000    00000800     UNINITIALIZED
                  08022000    00000800     --HOLE--

.STACK_DATA_und
*          0    08022800    00000800     UNINITIALIZED
                  08022800    00000800     --HOLE--

08020000  StackModeABT
08020800  StackModeFIQ
08021000  StackModeIRQ
08021800  StackModeSVC
08022000  StackModeSYS
08022800  StackModeUND


    What makes such misalignments?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 196816 points

    Hi Koichiro-san,

    The RUN_START addresses are generated by linker. The addresses may not be aligned to statement order in linker cmd file.

  • 0 in reply to QJ Wang
    TI__Mastermind 22935 points

    Hi QJ,

    QJ Wang said:
    The addresses may not be aligned to statement order in linker cmd file.

    Do you mean the address mismatch is not a problem at all?

    Could you also answer to below point?

    Koichiro Tashiro said:
    As we discussed, Safety Library configures SVC, FIQ, IRQ, ABT, UND and SYS. Total 6 stacks.
    On the other hand, HalCoGen does not have SYS stack, but it has USR stack. Total 6 stacks.
    According to ARM R5 TRM, there are 7 operation modes, USR, SVC, FIQ, IRQ, ABT, UND and SYS. Total 7.

    What is correct configuration to use RM57L?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 196816 points

    SYS and USR use the same stack space.

    Koichiro Tashiro said:
    Do you mean the address mismatch is not a problem at all?

    No problem.