• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 31 subscribers
  • Views 410 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C1294NCPDT: Lowest power mode that retains RAM?

adevries
Intellectual 945 points
Part Number: TM4C1294NCPDT

Hello TI Forum,

I am developing an application that uses a TM4C129 microcontroller. At certain points, I would like the microcontroller to enter the lowest power mode possible while still retaining the SRAM. After reading the datasheet, I still can't tell what power configuration to use. I know that the hibernation module has 16 32-bit words of battery backed memory, but I need more memory than that. The datasheet isn't 100% clear which low-power modes will wipe the SRAM and which will retain it, so I'm hoping someone can help me figure this out.

Based on my reading, I don't think I want hibernation mode, because RAM appears to be lost. However, hibernation + VDD3ON mode seems to at least retain GPIO pin states, so maybe it also saves all RAM? But I'm not sure.

Bonus question: if the voltage drops low enough, will the microcontroller automatically turn off and erase everything before the voltage drops low enough to corrupt the RAM? Or do I need to worry about that myself? I'm concerned about the situation where the backup voltage droops so low the RAM gets corrupted, and then when primary power is reapplied, the microcontroller thinks it has valid data, but it's actually corrupted. Ideally, I'd like to retain the RAM for as long as possible, but wipe it if I hit some low-voltage threshold. That way, when primary power is applied, I either have valid data that was retained, or no data at all.

Thanks!

  • +1
    Guru 92251 points
    adevries said:
    However, hibernation + VDD3ON mode seems to at least retain GPIO pin states, so maybe it also saves all RAM?

    Section 7.3.3 System Implementation of the TM4C1294NCPDT datasheet contains the following:

    Using the VDD3ON mode, where VDD continues to be powered in hibernation, allowing the GPIO pins to retain their states, as shown in Figure 7-3 on page 537. In this mode, VDDC is powered off internally.

    Since VDDC is powered off internally when  hibernation + VDD3ON mode is used, that means the SRAM will also be powered off as it is VDDC which powers the internal logic.

    Therefore, the lowest power mode which preserves SRAM is deep-sleep.

    adevries said:
    Bonus question: if the voltage drops low enough, will the microcontroller automatically turn off and erase everything before the voltage drops low enough to corrupt the RAM?

    There is a brown-out detection circuit, whose default behaviour is to generate a full power-on-reset (POR) if VDD drops below the brown-out threshold voltage. While a POR doesn't clear the SRAM, a reset can cause your program to invalidate the SRAM content (as opposed to a wake-up from deep-sleep in which the SRAM contents will be preserved).

  • 0
    TI__Guru*** 135355 points

    Hi Chester,

    Thanks for helping with this one, great answer as usual!

    Adevries, any further questions here that we can help with?

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Ralph Jacobi
    Intellectual 945 points

    Hi Ralph,

    That response answered my question. Thank you!

  • 0 in reply to Chester Gillon
    Intellectual 945 points

    Hi Chester,

    Thanks, that's exactly what I was wondering!