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AM2432: GPMC DMA

Mari Tsunoda
Expert 5726 points
Part Number: AM2432

Hi Team,

My customer has questions regarding GPMC as below. 

  1. In DMA Wrapped settings, when setting GPMC to Incrementing (not wrapped) Csi, what will happen to GPMC_AD output when 16bit/16byte burst write and 128 byte write? (Which of the three below?)
    1. Valid address becomes the same address every burst writing cycle
    2. Valid address becomes +16bytes address every burst writing cycle
    3. None of the above
  2. When the GPMC_WAIT pin is valid, what is the relationship between CYCLETIME counter and GPMC setting values?
    1. When the CYCLETIME counter is on freeze, is it accurate to say that RDACCESSTIME, WRACCESSTIME, PAGEBURSTACCESSTIME are affected? Or will CSONTIME and CSOFFTIME also be affected when CYCLETIME counter is on freeze?

Best regards,

Mari Tsunoda

  • 0
    TI__Expert 5726 points

    Hi,

    The customer updated their question to be more specific. Please read below. Leaving the questions above for reference (no need to answer).

    1. We use GPMC for Multiplexed Address Data 16-Bit Devices.
      Wrapped and Incrementing burst transfer to the FIFO or internal memory of the FPGA connected to the outside of the CPU.
      If DMA setting is Wrapped and GPMC setting is Incrementing, is the GPMC output address incremented when DMA is transferred to the GPMC address?
    2. Are the settings and timing charts in the attached file correct?
      1. CS0 - Syncronous Single Read Access
      2. CS0 - Syncronous Single Write Access
      3. CS1 - Syncronous Burst Read Access
      4. CS1 - Syncronous Burst Write Access

    Reference.xlsx

    Best regards,

    Mari Tsunoda

  • 0 in reply to Mari Tsunoda
    TI__Mastermind 30110 points

    Hi Tsunoda-san,

    Normally with synchronous write/read the GPMC address latch phase will occur at the beginning of each GPMC burst only and incremented by (ATTACHEDDEVICEPAGELENGTH * DEVICESIZE) bytes each time it appears on the bus (ie. 8x 16-bit words = 16 bytes, 0x10 address increments).
        
    If configured the ADVn signal will pulse during the address phase of the GPMC read/write burst cycle. I see you do not use it, but it may be a valuable debug signal to probe.
       
    I have reviewed the settings and timing charts.
        
    BASEADDRESS    20h    and 21h
        These base address bit fields will have to change to 10h and 11h to match the base address of GPMCdata space on AM243x @ 0x50000000.
        
    WAITREADMONITORING    1    1
    WAITWRITEMONITORING    1    1
    WAITMONITORINGTIME    0b00    0b00
        Wait monitoring support is limited to a WaitMonitoringTime value > 0 for burst writes. FPGA should give WAIT to GPMC at least 1 FCLK cycle before the write access - don't give WAIT in the same FCLK clock cycle as the access. WAIT will still need to satisfy setup time before rising CLK edge used to latch it.
        See Datasheet Table 7-52. GPMC and NOR Flash Timing Requirements — Synchronous Mode Note 3
        See TRM 12.3.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
        
    Regards,
    Mark

  • 0 in reply to Mark M
    TI__Expert 5726 points

    Hi Mark,

    Thanks for your reply.

    They have a few follow-up questions as below.

    1. Regarding BASEADDRESS 10h and 11h, GPMC0_DATA(=0x2000_0000) of TRM 12.3.3.4.12 GPMC Memory Regions is wrong. We must see GPMC0_DATA(=0x5000_0000) of TRM 2.1 Main Domain Memory Map.
    Is my understanding correct?

    2. Is it correct that the addresses appear on the bus as GPMC_AD(a) (image below)?

    Best regards,

    Mari Tsunoda

  • 0 in reply to Mari Tsunoda
    TI__Expert 5726 points

    Hi Mark,

    Any update on this?

    Best regards,

    Mari Tsunoda

  • 0 in reply to Mari Tsunoda
    TI__Mastermind 30110 points

    Hi

    1. Correct. Thanks for pointing out that TRM 12.3.3.4.12 GPMC Memory Regions is wrong.

    Refer instead to Table 2-1. MAIN Domain Memory Map

    GPMC0_DATA 0x050000000 0x057FFFFFF 128 MB

    2. No I think the address should come out like the GPMC_AD(b) picture. A different address appears at the beginning of each GPMC burst.

    Regards,
    Mark