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EK-TM4C1294XL: Reading 64 bit on each data line from QSOI by using QSSI

Mostafa Koraei
Intellectual 445 points
Part Number: EK-TM4C1294XL

Hi TI,

I am trying to read AD7768 by EK-TM4C1294. The data interface is a QSPI that has a Data Ready signal, DCLK and four Data lines.

I am trying to use ssi_quad_mode.c  example from TI. Based on the TM4C1294 datasheet I think the Data Ready signal should be considered as SSInFss.

However, in the datasheet it is mentioned that I can capture 4 to 16 bit after SSInFss comes down while here I need to capture 32 to 64 bits before receive the next DRDY from ADC.

Do you have any suggestion that how I can read a QSPI with long frames like 32,64 or even more?

I am using TI-RTOS, but I have merged the ssi_quad_mode.c in my project. It is also possible if there is not any work around it I drop the RTOS and just write bare metal code but I prefer to kee it as the last option.

Best regards,

Mostafa

  • 0
    TI__Guru**** 191826 points

    Hi,

    Mostafa Koraei said:

    However, in the datasheet it is mentioned that I can capture 4 to 16 bit after SSInFss comes down while here I need to capture 32 to 64 bits before receive the next DRDY from ADC.

    Do you have any suggestion that how I can read a QSPI with long frames like 32,64 or even more?

    You can call the MAP_SSIAdvFrameHoldEnable() API to hold the Fss signal active during transfers until the last data is written/read.  If you are reading 64 bits then you would configure the SSI for 16 bits and use the Frame Hold feature to hold the Fss active the the four 16-bit transfers. At the end of the fourth 16- bit transfer the Fss will be deasserted. Please refer to C:\ti\TivaWare_C_Series-2.2.0.295\examples\boards\ek-tm4c1294xl\ssi_quad_mode example.

    Mostafa Koraei said:
    I am using TI-RTOS, but I have merged the ssi_quad_mode.c in my project. It is also possible if there is not any work around it I drop the RTOS and just write bare metal code but I prefer to kee it as the last option.

    I don't think TI-RTOS SPI drivers support Quad-mode and Frame Hold features. However, you can use directly the TivaWare SSI drivers within TI-RTOS. 

  • 0 in reply to Charles Tsai
    Intellectual 445 points

    Hi Charles,

    Sorry, I have been a little confuesd :) 

    The QSSI of the MCU is in the slave mode and as I understood SSInFss is an input signal to slave QSSI. If I call MAP_SSIAdvFrameHoldEnable(), then how to find that I have received 16 bits to be able to count for 64 bits.

    I am using C:\ti\TivaWare_C_Series-2.2.0.295\examples\boards\ek-tm4c1294xl\ssi_quad_mode example.

    Another question is that if how I can assign differnt pins to sclk, ssinfss or data lines?

    - Mostafa

  • 0 in reply to Mostafa Koraei
    TI__Guru**** 191826 points

    Hi Mostafa,

    Mostafa Koraei said:
    The QSSI of the MCU is in the slave mode and as I understood SSInFss is an input signal to slave QSSI. If I call MAP_SSIAdvFrameHoldEnable(), then how to find that I have received 16 bits to be able to count for 64 bits.

    I'm also confused. How can AD7768 be the master? In my opinion it is just a sensor with SPI interface. MCU is reading data from the sensor. if this is the case then MCU is the master and AD7768 is the slave. I will suggest you consult with AD7768 vendor for clarification if otherwise. They may have example code for interfacing with their device although not necessarily using TM4C129 as the MCU. If my understanding is wrong and QSSI must be used as a slave then the Frame Hold I talked about will not work. Please note that if AD7768 is the master then it must be driving clock, SSInFss and data to the MCU. In this case, SSInFss is controlled by AD7768. You can't have MCU drive SSInFss as a slave while AD7768 as a master drive the clock and data. Again, I have no experience with AD7768. 

  • 0 in reply to Charles Tsai
    Intellectual 445 points

    Hi Charles,

    Thanks for your explanation. Yes, AD7768 is master. It sends sclk, DRDY (that has a one cycle pulse in beginning of each transfer that can be 32, 64 or more bits )and 4 data lines that are synced with sclk.

    I can forget QSPI and use TDM on AD7768 to receive all chanels on one data line and then it will be a normal SPI.

    However, I am wondering how I can have a normal slave SPI on TM4C1294. Because there is still one pin  SSInFss that should come from Master.

    I ound in the datasheet that:  The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave
    select.

    So, I think it should be a chip select for TM4C in slave mode and I can connect DRDY to it. However, again I have problem with the 4 to 16 bit limitation when it comes to receiving data. because 

    AD7768 sets DRDY low between two samples that can be even hundreds of bits.

    I have witten a driver for this ADC in FPGA before and it went well, but here I don't know how I can have a normal slave SPI in TM4C1294 without caring about SSInFss like 

    other MCU/DSPs that you can read CS from any pin and start reading from master while it sends you clock and data.

    Thanks in advance,

    Mostafa

  • 0 in reply to Mostafa Koraei
    TI__Guru**** 191826 points

    Hi Mostafa,

    Mostafa Koraei said:

    I can forget QSPI and use TDM on AD7768 to receive all chanels on one data line and then it will be a normal SPI.

    However, I am wondering how I can have a normal slave SPI on TM4C1294. Because there is still one pin  SSInFss that should come from Master.

    I ound in the datasheet that:  The Freescale SPI interface is a four-wire interface where the SSInFss signal behaves as a slave
    select.

    Ok. If AD7768 is a master then it needs to provide the chip select which is the the SSInFss to the MCU. 

    Mostafa Koraei said:
    So, I think it should be a chip select for TM4C in slave mode and I can connect DRDY to it. However, again I have problem with the 4 to 16 bit limitation when it comes to receiving data. because 

    Let's say AD7768 wants to send to the MCU 64 bits of data. You can configure the MCU as a slave for 16-bit of character length. For each 16 bits of data shifted in, it will be saved to the RXFIFO. For 64 bits of data, there will be four 16-bit of words saved in the RXFIFO. It is your application which needs to process (e.g. combine or concatenate these four 16-bit data ) these received data into useful information.