Hi Team,
I received this question from one of my customers.
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Setting primary bootmode:SPI and backup bootmode:UART, on this condition, if we cut CS0 line of SPI flash(ex. using DIPSW on board), what happens? we expect the behavior of ROM on CPU as follows:
primary boot failed so, try backup boot.background of the question:
we expect usages as follow:
usually boot from SPI flash. when we want to update bootcode on SPI flash, boot with special bootcode via UART, then re-write SPI flash using UART-booted bootcode. - See AM64/AM243x TRM igure 4-3. Boot Process.
When SPI Flash doesn't response on SPI boot, how long does it take to be judged as "Ingtegrity check No"?
On Figure 4-3, "DSMC Watchdog Timer Timeout?(3min)" means ROM code continues primary boot and backup boot for 3 minutes. is it right?
Best regards,
Mari Tsunoda