RM57L843: Probe erasing flash via uniflash or CCS, but the unused contents are not all 0xff?

Hello TI engineer:

I had solved " Bootloader erase flash using F021 API, but the contents are not all 0xff?" problem.

RM57L843: Bootloader erase flash using F021 API, but the contents are not all 0xff? - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thank you.

But I found when I debugging the program, erasing and programming the codes into flash via probe on CCS, the unused contents of flash are also not all 0xff? Same problem is met using uniflash.

How to fix it? My linker cmd as following: 

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
ECC {
	algoL2R5F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */
	hamming_mask = R4 /* Use R4/R5 build in Mask */
	parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */
	mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */
}
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFD0	vfill=0xffffffff
    SW_VERSION	(RX) 	: origin=0x001FFFF0 length=0x00000008	/* Software Version */
    GOLDEN_CRC	(RX)	: origin=0x001FFFF8 length=0x00000008	/* golden FLASH CRC */
    FLASH1  (RX) : origin=0x00200000 length=0x00200000	vfill=0xffffffff
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007EB00
    FEE     (RW) : origin=0xF0200000 length=0x00020000	vfill=0xffffffff
	/* Bank 0 ECC */
	ECC_VEC (R)     : origin=(0xF0400000 + (start(VECTORS) >> 3))
					  length=(size(VECTORS) >> 3)
					  ECC={algorithm=algoL2R5F021,input_range=VECTORS}

	ECC_FLA0 (R)    : origin=(0xF0400000 + (start(FLASH0) >> 3))
					  length=(size(FLASH0) >> 3)
					  ECC={algorithm=algoL2R5F021,input_range=FLASH0}
	/* Bank 1 ECC */
	ECC_FLA1 (R)    : origin=(0xF0400000 + (start(FLASH1) >> 3))
					  length=(size(FLASH1) >> 3)
					  ECC={algorithm=algoL2R5F021,input_range=FLASH1}
	/* Bank 7 ECC */
	ECC_FLA7 (R)    : origin=0xF0100000
					  length=(size(FEE) >> 3)
					  ECC={algorithm=algoL2R5F021,input_range=FEE}

/* USER CODE BEGIN (3) */
/* USER CODE END */
}

/* USER CODE BEGIN (4) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
    .intvecs 	: {} palign=8 > VECTORS
    .text    		: {} palign=8 > FLASH0
    .const   		: {} palign=8 > FLASH0
    .cinit    		: {} palign=8 > FLASH0
    .pinit    		: {} palign=8 > FLASH0
    GROUP
	{
        .TI.ramfunc
        { -l rtsv7R4_T_le_v3D16_eabi.lib<memcmp.c.obj>}
//        { -l rtsv7R4_T_le_v3D16_eabi.lib<memcpy_t2.asm.obj>}
        { -l F021_API_CortexR4_LE_L2FMC_V3D16.lib}

	}LOAD > FLASH0
    RUN > RAM
    LOAD_START(_RamfuncsLoadStart)
    LOAD_SIZE(_RamfuncsLoadSize)
    LOAD_END(_RamfuncsLoadEnd)
    RUN_START(_RamfuncsRunStart)
    RUN_SIZE(_RamfuncsRunSize)
    RUN_END(_RamfuncsRunEnd)
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

/* USER CODE BEGIN (6) */
	.stack	 : {} > STACKS
	SW_VERSION_DATA		: START(ulSWVERSIONStartAddr) > SW_VERSION
	GOLDEN_CRC_DATA		: START(ulGOLDENCRCStartAddr) > GOLDEN_CRC
/* USER CODE END */
}