• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 30 subscribers
  • Views 259 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LS3137: On interrupt freezing during active flash operation

TMS570LS3137: Regarding interrupt freeze during active flash operation

Sh.Sasaki
Guru 13625 points
Part Number: TMS570LS3137

Hi, 

I have a question related to the link below.

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/760768/tms570ls3137-on-interrupt-freezing-during-active-flash-operation

Is it possible for interrupts to freeze if the CPU accesses a sector that ends with an error due to erasing or writing?

The link above prohibits the CPU from accessing sectors that are undergoing flash operations such as erasing.

The question in this thread is about accessing the sector after the flush operation ended with an error.

Best regards,
Sasaki

  • 0
    TI__Guru**** 196886 points

    Hi Sasaki-san,

    I don't understand this question. Reading flash sector while this sector is being erased will stall the CPU util the erase operation completes.

  • 0 in reply to QJ Wang
    Guru 13625 points

    Hi Wang-san,

    I'm sorry my question is confusing.

    The question is, is there a possibility that interrupts will freeze if erase or write is performed again on a sector that has completed an error due to erase or write?
    I don't think this interrupt freeze will occur because the internal flash controller is stopped for sectors that end in error due to erasing or writing. Is this idea correct?

    Best regads,
    Sasaki

  • +1 in reply to Sh.Sasaki
    TI__Guru**** 196886 points

    Hi Sasaki-san,

    If CPU tries to read from the flash bank that is being programmed or erased, the read access will be stalled until the program or erase operation has completed.

    If your interrupt vectors or the code that the vectors jump to reside in the same bank as the Flash operation is occurring, the CPU will stall until the Flash operation is complete 

  • 0 in reply to QJ Wang
    Guru 13625 points

    Hi Wang-san,

    Thank you for your reply.

    In other words, if FMSTAT BUSY is not set, interrupt freeze will not occur. Is this correct?

    Best regards,
    Sasaki

  • +1 in reply to Sh.Sasaki
    TI__Guru**** 196886 points

    Hi Sasaki-san,

    Yes, you are correct. If BUSY is not set, there is no ongoing flash erase/program/suspend operation.