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Original question:

Starterware/TM4C129XNCZAD: EPI Bus Read and Write Priority

TM4C129XNCZAD: Data Corruption when reading from external SDRAM for LCD module

Yash Pandya
Prodigy 90 points
Part Number: TM4C129XNCZAD

Hello Everyone,

I am driving 800x480 16 bit LCD using custom board with TM4C129X microcontroller. I have added external 8MB SDRAM and connected it with EPI as external SDRAM. And I'm facing a lot of issues.

My system clock is running at 120MHz and LCD clock is at 24MHz and EPI at 60MHz.

1. My LCD doesn't show anything  until I set Burst size as 0x3 or 0x4 in LCD_DMACTL register. When I am not using external SDRAM my LCD worked with 0x2 value also. I want to know how does his affect the screen and what all parameters decide the value of burst size and DMA FIFO threshold.

2. As datasheet mentioned: When using the LCD with EPI to interface to external memory, the external code address space 0x1000.0000 must be selected by programing the ECADR field to 0x1 in the EPI Address Map (EPIADDRMAP) register at EPI offset 0x01C. When I am using 0x1000.0000 address for SDRAM there are a lot of data corruption on screen but when I switched the address to 0x6000.0000 data corruption drops significantly but still there are pixels showing incorrect value. How to improve this.

3. When I am driving EPI at 60MHz data corruption is more comparative to EPI at 120MHz. But datasheet recommend it to run at 60MHz. Why is this happening?

4. Overall I wanted to ask how to reduce the data corruption so that I can run my LCD very smoothly. Is there any register that I might have forget to set that my solve my issue.

5. And when using external SDRAM to drive LCD, how should we connect it to EPI: as External SDRAM or HOST 16 bus.

Thanks in Advance for your help.

  

  • 0
    TI__Guru**** 191486 points

    Hi, 

      I'm not really an expert in LCD and neither the EPI. I will try my best to answer your questions. Before I try to answer your questions, can you answer me if you are using the Raster or LIDD mode? What is the make and model of the LCD display you are using?

    Yash Pandya said:
    1. My LCD doesn't show anything  until I set Burst size as 0x3 or 0x4 in LCD_DMACTL register. When I am not using external SDRAM my LCD worked with 0x2 value also. I want to know how does his affect the screen and what all parameters decide the value of burst size and DMA FIFO threshold.

    I suppose reading from external memory will take longer time than from internal memory. Therefore, 0x3/0x4 for a larger burst size will work better for the DMA to burst more data from the external memory. Are you using ping-pong mode? Please see below description. I will advice you use ping-pong mode for the DMA to read from two different frame buffers. 

    21.3.2 LCD DMA Engine
    The LCD DMA engine provides the capability to output graphics data to constantly refresh the
    external LCD display, without burdening the CPU, via interrupts or a firmware timer. It operates on
    one or two frame buffers, which are set up during initialization. Using two frame buffers (ping-pong
    buffers) enables the simultaneous operation of outputting the current video frame to the external
    display and updating the next video frame. The ping-pong buffering approach is preferred in most
    applications.

    Yash Pandya said:
    2. As datasheet mentioned: When using the LCD with EPI to interface to external memory, the external code address space 0x1000.0000 must be selected by programing the ECADR field to 0x1 in the EPI Address Map (EPIADDRMAP) register at EPI offset 0x01C. When I am using 0x1000.0000 address for SDRAM there are a lot of data corruption on screen but when I switched the address to 0x6000.0000 data corruption drops significantly but still there are pixels showing incorrect value. How to improve this

    My understanding is that the SDRAM is used to store your frame buffers. If this is the case, why would you want to configure SDRAM for code fetch. Shouldn't you use SDRAM for data only? In another word, run your code from  internal flash and read frame buffers from SDRAM. 

    Yash Pandya said:
    3. When I am driving EPI at 60MHz data corruption is more comparative to EPI at 120MHz. But datasheet recommend it to run at 60MHz. Why is this happening?

    You violate the EPI timing if you use 120Mhz. See below. 

    Yash Pandya said:
    4. Overall I wanted to ask how to reduce the data corruption so that I can run my LCD very smoothly. Is there any register that I might have forget to set that my solve my issue.

    Please address the above points I answered to see if you improve the issue. 

    Yash Pandya said:

    5. And when using external SDRAM to drive LCD, how should we connect it to EPI: as External SDRAM or HOST 16 bus.

    If you have an SDRAM memory then you need to configure EPI for SDRAM interface. See example at C:\ti\TivaWare_C_Series-2.2.0.295\examples\peripherals\epi\sdram.c

  • 0
    Prodigy 90 points

    Do you have any example code that will help me to understand how to implement ping pong mode.

  • 0 in reply to Charles Tsai
    Prodigy 90 points

    This is how I initialize EPI module. Do I need to set other registers to make it run smoothly. I am using RASTER mode and my LCD is 16bpp. 

    SYSCTL_RCGCEPI_R = 1;
    EPI0_BAUD_R = 1;
    EPI0_CFG_R = 0x00000011;
    while(EPI0_STAT_R & (1<<6));
    EPI0_SDRAMCFG_R = (0x3<<30)|(748<<16)|(1);
    EPI0_ADDRMAP_R = 0x009;
    ram = (uint16_t *)0x60000000;

  • 0 in reply to Yash Pandya
    TI__Guru**** 191486 points

    Hi,

    Yash Pandya said:
    Do you have any example code that will help me to understand how to implement ping pong mode.

    Sorry, we don't have any examples. But if you look at the registers, it should be just to enable two frame buffers and provide the base address to reach frame buffer. See below registers.

    Yash Pandya said:
    This is how I initialize EPI module. Do I need to set other registers to make it run smoothly. I am using RASTER mode and my LCD is 16bpp. 

    I don't really spot anything wrong with your EPI setting for SDRAM. 

  • 0 in reply to Charles Tsai
    Prodigy 90 points

    In there any way to put delay between Frame Buffer 0 and Frame Buffer 1 while using ping pong mode.

  • 0 in reply to Yash Pandya
    TI__Guru**** 191486 points

    Hi,

      First of all, I want to know if ping-pong mode is helping your situation. Can you confirm?

    Yash Pandya said:
    In there any way to put delay between Frame Buffer 0 and Frame Buffer 1 while using ping pong mode.

      I don't think so. The frame buffer 0/1 during ping-pong mode transfer is carried out by the built-in DMA module. CPU cannot intervene other than to enable or disable it. Why do you want to insert delay between frame buffer 0 and 1? Is the transfer too fast? Why would it be a problem if it is too fast? Or are you writing to the LCD interface too slowly?

      When either frame buffer 0 or 1 transfer is done the interrupt is generated and EOF0 or EOF1 will be set accordingly. 

    Frame transfer completed: When one frame of data is transferred completely, the DONE bit in
    the LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set. This bit is cleared
    by disabling the Raster Controller (clearing the LCDEN bit in LCD Raster Control
    (LCDRASTRCTL) register). The EOF0 and EOF1 bits in LCD Interrupt Raw Status and Set
    Register (LCDRISSET) register are set accordingly.

      Please check if you have a under-run error or any type of errors? Please confirm that your LCDCP is indeed running at the correct frequency. What frequency do you have right now for the pixel clock (LCDCP)?

    Output FIFO under-run: This interrupt occurs when the DMA engine cannot keep up with the
    data rate consumed by the LCD (which is determined by the LCDCP.) This is likely due to a
    system memory throughput issue or an incorrect LCDCP setting. The FIFOU bit in LCD Interrupt
    Raw Status and Set Register (LCDRISSET) register is set when this error occurs. This bit is
    cleared by disabling the Raster Controller, that is clearing the LCDEN bit in LCD Raster Control
    (LCDRASTRCTL) register.

    Lastly, I know that the datasheet has the below note. However, I do not understand why it is required the EPI module to be also configured for code space. See below. Do you see any difference in your LCD operation if you set EPI ECADR to 0x1 vs 0x0?

    Note: When using the LCD with EPI to interface to external memory, the external code address
    space 0x1000.0000 must be selected by programing the ECADR field to 0x1 in the EPI
    Address Map (EPIADDRMAP) register at EPI offset 0x01C.

  • 0 in reply to Charles Tsai
    Prodigy 90 points

    No I'm still getting underflow error in ping pong mode.

  • +1 in reply to Yash Pandya
    TI__Guru**** 191486 points

    How big is your frame buffer? 

    What is your pixel clock frequency?

    Can you do some measurement on how much time it takes to read the frame buffer on the external SDRAM vs the time it takes to write to the LCD interface. 

    For experiment, I will also suggest you leave out the LCD and focus on the SDRAM access and make sure you are running at the fast throughput possible to retrieve data from SDRAM.

  • 0 in reply to Charles Tsai
    Prodigy 90 points

    My frame buffer is 800x480x4 byte long and My pixel clock freq is 24MHz.

    I calculate the time between eofb0 interrupt and rrasterdone interrupt and that was 25us and and time between two rrasterdone interrupt is 21201us. 

  • 0 in reply to Yash Pandya
    Prodigy 90 points

    And it took me 100ms to do all calculation and prepare 1 frame.

    How should I configure things so that I wont face any underflow  error.

  • 0 in reply to Yash Pandya
    TI__Guru**** 191486 points
    Yash Pandya said:

    My frame buffer is 800x480x4 byte long and My pixel clock freq is 24MHz.

    Will running the pixel clock at 60Mhz help or anything higher than 24MHz?

    Yash Pandya said:
    I calculate the time between eofb0 interrupt and rrasterdone interrupt and that was 25us and and time between two rrasterdone interrupt is 21201us

    Can you draw a timing diagram so I have some idea what is going?

    Also a question is if you are trying to create a video on the LCD panel or just a still image?

    Yash Pandya said:
    And it took me 100ms to do all calculation and prepare 1 frame.

    I think a timing diagram will really help. Show how much time you need to prepare one frame, how much time you need to read one frame buffer on SDRAM and how much time you need to complete the write to the LCD panel. 

    Yash Pandya said:
    How should I configure things so that I wont face any underflow  error.

    Are you sure it is an underflow. Underflow means you are reading the SDRAM too slowly and you are writing to LCD panel too fast. Is this really what happen? If this is really the case, can you slow down the pixel clock from 24Mhz to something lower?