AM2634: AM2634 FSI Transmit Clock Speed Question

ngrkus

Part Number: AM2634

Hi,

I am using the Sitara AM2634 on the Evaluation Kit desribed in SPRUJ09. I am trying to test the FSI performance. I did copy from the SDK 8.2.0.28 the example "fsi_loopback_polling_am263x-cc_r5fss0-0_nortos_ti-arm-clang" and did change to the FSI channel 2 in order to be able to measure the signals on J6 of the evaluation kit. Additionally I did disable the internal loopback. Running the program returns success after 100 messages or so.

However when I measure the clock on J6 of the Evalukation Kit (AM263x Control Card HW) I do get 3 MHz(!) instead of the the 50 MHz it should be according to the comments in this example. Actually I may make something wrong, however I did not touch the clock settings of the SoC. In the console window of CCS it does state:

CS_DAP_0: GEL Output: *********************************************************
CS_DAP_0: GEL Output: **********All R5F Cores Released for program load********
CS_DAP_0: GEL Output: *********************************************************
CS_DAP_0: GEL Output: SYS_CLK DIVBY2
CS_DAP_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
CS_DAP_0: GEL Output:

CLK Programmed R5F=400MHz and SYS_CLK=200MHz

Therefore I do assume that the system clock of the SoC is 200 MHz. Dividing this by four thats what the code of the example does would give 50 MHz. I do measure 3 MHz on J6 ... When I try to display the contents of the FSI 2 Tx Clock Control Register within CCS I do get: "00000012" at the address 0x502A0004. According to the TRM and registers documentation this makes sense. Clock is enabled and the 'PRESCALE_VAL' is 4 which is needed to get the 50MHz clock. I do run the sample code on CPU3 instead of CPU0. However I do assume this does not matter.

Any idea of what I could check next would be appreciated? As always we are a little bit on pressure with design decisions for this type of SoC for our project...

Markus

over 3 years ago

0 ngrkus over 3 years ago

Expert 1020 points

Digging a little bit deeper I saw that within the syscfg tool that the clock is being used is named (FSI Rx/Tx Other Dependencies ...) 'WUCPUCLK'. This is the on-board clock source that is 25MHz. This does explain why I do get 3.125MHz instead of the required 50MHz using one of the FSI examples from the SDK. However changing the input clock source to for example SYS_CLK does not change anything.

I wonder when in the boot/startup process the control module register is being set (MSS_RCM_CONTROLSS_PLL_CLK_SRC_SEL Register. Pg 357 of the register documentation SPRUJ42 -- March 2022). Rebuilding the project does generate a source file named 'ti_power_clock_config.c'...

A hint on the how to setup the FSI's using the PLLRAWCLK or the SYS_CLK would be well appreciated.

0 Frank Livingston over 3 years ago in reply to ngrkus

TI__Mastermind 29778 points

Hi Markus,

I'm looking into this and will get back with you shortly.

Regards,
Frank

0 Frank Livingston over 3 years ago in reply to ngrkus

TI__Mastermind 29778 points

Hi Markus,

I agree with your observations. The issue seems to be that Syscfg isn't generating the code to configure the clock mux selecting the input to the FSI functional clock. As a result, the FSI functional clock is set to 25 MHz.

This seems like a SW bug to me. I'll follow up with the SW development team to confirm.

I was able to get the correct FSI function clock by adding this code to main() just before the call to fsi_loopback_main():

#include <drivers/soc.h>

SOC_controlModuleUnlockMMR(0, MSS_RCM_PARTITION0);
SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId_CONTROLSS_PLL , SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, 400000000);
SOC_controlModuleLockMMR(0, MSS_RCM_PARTITION0);

Can you please see if this works for you?

Regards,
Frank

0 ngrkus over 3 years ago in reply to Frank Livingston

Expert 1020 points

Hi Frank,

indeed it works now. This is good for now. Thank you.

BTW I did discover another issue with respect to the FSI. When I select for example the SYS_CLK as the clock source for the FSI blocks, it get the impression (osc. measurements) that the clock speed is always 1/2 the input clock. In the case of the SYS_CLK it is always 100MHz. This is regardless of the prescalier value. Can you please double check on this? In my view the actual documentation is a little bit ambiguous on this. By reading the documentation, I got the impression that the TxClk prescalier is after the clock source selection be it PLLRAWCLK or be it SYS_CLK. Now I think the prescalier is just after the PLLRAWCLK selection but not after the SYS_CLK which is 200MHz in our case.

Markus

0 Frank Livingston over 3 years ago in reply to ngrkus

TI__Mastermind 29778 points

Hi Markus,

I'm looping in a colleague to help with the clocking question.

Regards,
Frank

0 Fleenor over 3 years ago in reply to ngrkus

TI__Mastermind 24613 points

Hi Markus,

There are two clocks signals here that you should be aware of:

1) TXCLK (FSITX Interface Clock)

2) TXCLKIN (FSITX Interface Clock*2 or FSI-SPI-Signaling Mode Clock)

This information can be understood from the CONTROLSS_FSITX:TX_CLK_CTRL register descriptions (screenshot below for reference).

The key here is the following note:

TXCLKIN = Input clock / PRESCALE_VAL
In FSI mode: TXCLK = TXCLKIN / 2
In SPI mode: TXCLK = TXCLKIN

Clock Divider Prescale Value
The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate.

0h (R/W) = Reserved
1h (R/W) = Input clock /1
2h (R/W) = Input clock /2
3h (R/W) = Input clock /3
4h (R/W) = Input clock /4
...
FFh (R/W) = Input clock /255

TXCLKIN = Input clock / PRESCALE_VAL
In FSI mode: TXCLK = TXCLKIN / 2
In SPI mode: TXCLK = TXCLKIN

Best Regards,

Zackary Fleenor

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AM2634: AM2634 FSI Transmit Clock Speed Question