• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 882 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

STC on RTOS

Burim Aliu
Intellectual 510 points
Other Parts Discussed in Thread: HALCOGEN

Hi 

I hope somebody can help me with an explanation about a problem with STC/Test 

1. I have configured the RTOS and it is correctly running in the TMS570

2. I have created many task which do different operations and in one of them should run the STC core test

3. After the Task with the STC core test  is scheduled to run i protect this task with taskENTER_CRITICAL() which don't allows Preemptive context switches  and release after finished with taskEXIT_CRITICAL() 

My Problem is that i can't debug to see which error happens because the STC never returns back.

I store the complete context(registers, stac etc) of the core before running the STC test and restore it after finishing.

Must i take care of the actual Task of the RTOS in which the test is running?

Any explanation is welcome :)

Regards Burim

  • 0
    TI__Intellectual 2285 points

    Hi Burim,

    The STC test when initiated may end with the reset when test completes, so we cant expect it to return.

    You may check the SYS ESR register(in system module) to know if the system got reset and the STC GSTAT register to know the status of the LBIST test.

    - Partip

     

  • 0 in reply to Pratip Kumar
    Intellectual 510 points

    Hi Partip,

    Yes clearly it generates a reset and the if the reset is generated by the STC the fifth bit in SystemExceptionStatusRegister[5] is set to 1

    But is any possibility to debug, because after the reset all breakpoint etc are removed?

    And one concern of me is if i have integrated it correctly in the RTOS kernel? 

    Regards 

    Burim

  • 0 in reply to Burim Aliu
    TI__Intellectual 2285 points

    Hi Burim,

    Once the test kick starts the STC takes over and connection to micro is lost. We may have to wait for the CPU reset and look into the STC status registers.

    if((SYSESR & 0x20) == 1)

    {

     

     

    //clear CPU RST Bit

     

     

     

     

    SYS_Ptr->SYSESR_UN.SYSESR_ST.MPCRST_B1 = 1;

     

    //SYSESR = 0x01;

     

     

    switch(STC_Ptr->STCGSTAT_UN.STCGSTAT_UL & 0x3)

    {

     

     

    Case 0: //Test Not Yet Started Don't Stop Go Ahead

     

     

     

     

    break;

     

     

     

     

    case 1://Test case Completed Sucessfully

     

    error = 0;

     

     

     

    break;

     

     

     

     

    case 2://Test case Not Completed

     

    error = 2;

     

     

     

    break;

     

     

     

     

    case 3://Test case Completed and Failed

     

    error = 3;

     

     

     

    break;

     

     

     

     

    default : for(;;);

     

    }

    By the way which OS are you using ? Is it FREERTOS  within HALCogen ?

    - Pratip

     

  • 0 in reply to Pratip Kumar
    Intellectual 510 points

    Hi Pratip,

    Yes I am using the FreeRTOS generated from the HALCogen

    Burim

  • 0 in reply to Burim Aliu
    TI__Intellectual 1460 points

    Burim,

    you can debug by adding and asm infinitie loop at the beginning of reset handler _c_int00.

    asm(" b #-8"); or asm(" b $"); should work.

    This stops excecution after reset.

    Now you can restore your breakpoints and carry on excecution by using the set PC option of the debugger.

     

    It is better to user a supervisor call to start the core test rather than starting it from a task.

    Next version of HALCoGen supports application SVC's in FreeRTOS.

     

    Cheers

    Marcus