GPIO_clearBankIntrStatus looks erroneous to me

Philip Schröder

Hello, as I am currently using bank interrupts for GPIO banks and was about to clear the banks in my ISR,
I wondered, why said function would need its third parameter, the interrupt status.

The implementation here in our SDK is the following one:

static inline void GPIO_clearBankIntrStatus(uint32_t baseAddr,
                                            uint32_t bankNum,
                                            uint32_t intrStatus)
{
    uint32_t                regIdx = bankNum >> 1U;
    volatile CSL_GpioRegs*  hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);

    /* Clear the interrupt status of gpio bank */
    intrStatus &= 0xFFFFU;
    if(bankNum & 0x01U)
    {
        intrStatus <<= GPIO_MAX_PIN_PER_BANK;   /* Odd number bank - upper 16-bits are used */
    }
    CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIdx].INTSTAT, intrStatus);

    return;
}

As far as I understand it, it doesn't clear the interrupt status but sets the interrupt status that is provided.

Then in the examples in examples/drivers/gpio/gpio_input_interrupt/gpio_input_interrupt.c it seems as if the code

    /* Get and clear bank interrupt status */
    intrStatus = GPIO_getBankIntrStatus(gGpioBaseAddr, bankNum);
    GPIO_clearBankIntrStatus(gGpioBaseAddr, bankNum, intrStatus);

simply sets the interrupt status which is already present.
As I see it, what I actually wanted was:

    /* Get and clear bank interrupt status */
    intrStatus = GPIO_getBankIntrStatus(gGpioBaseAddr, bankNum);
    GPIO_clearBankIntrStatus(gGpioBaseAddr, bankNum, 0U);

Or for future versions of the SDK, maybe ommit the last parameter at all and simply set intrStatus to 0U inside the function.
Am I correct here?
Thank you for your help.

Best regards

Philip.

over 3 years ago

0 LeonardEllis over 3 years ago

TI__Guru 71526 points

Hello Philip,

Please provide more information: what processor are you using?

Thank you,

~Leonard

0 Philip Schröder over 3 years ago

Prodigy 230 points

Aha, the TRM says:

So I am supposed to set the concerning bit position to 1.

Now the GPIO preprocessor defines seem not to be really well documented.
In drivers/gpio/v0/cslr_gpio.h there it seems at first glance that in CSL_GpioRegs there would be one bank register per bank.
As there are 9 banks and 9 BANK_REGISTERS.

But in drivers/gpio/v0/gpio.h it says:

/** \brief Maximum number of banks per instance/module */
#define GPIO_MAX_BANKS                  (9U)
/** \brief Maximum number of pins per bank */
#define GPIO_MAX_PIN_PER_BANK           (16U)
/** \brief Maximum number of pins per instance/module */
#define GPIO_MAX_PIN_PER_INSTANCE       (GPIO_MAX_BANKS * GPIO_MAX_PIN_PER_BANK)

/** \brief Number of banks per register */
#define GPIO_BANKS_PER_REG              (2U)
/** \brief Number of pins per register - 32 pins */
#define GPIO_PINS_PER_REG               (GPIO_BANKS_PER_REG * GPIO_MAX_PIN_PER_BANK)

But as there are only 9 banks and with 9 BANK_REGISTERS and each BANK_REGISTER having 2 banks.
That would be 18 banks.
My guess here is (which is the part that is missing in the documentation), that the BANK_REGISTERS hold the 9 banks of MAIN_GPIO0
followed by the banks of MAIN_GPIO1 module.
Then I am not sure what is with module MCU_GPIO0 though.

But then the definition of

/** \brief Maximum number of banks per instance/module */
#define GPIO_MAX_BANKS                  (9U)

Doesn't seem to make any sense, as there are clearly 18 banks with 9 registers and 2 banks per register.

0 Philip Schröder over 3 years ago in reply to LeonardEllis

Prodigy 230 points

[deleted]

0 Philip Schröder over 3 years ago in reply to Philip Schröder

Prodigy 230 points

I am using an am243x, I looked into the datasheet, is it right that the part number is:

XAM2434ASFGGAALV ?

0 Philip Schröder over 3 years ago

Prodigy 230 points

Ok,
I guess you get the interrupt status for the pin that originated it within the bank and then set the same status again, as by setting the corresponding bit to 1 the status is cleared,
like the TRM says it. Probably there is some internal dirty bit or something similar that is interpreted as the bit being set by software as to clear the interrupt status.

I was only confused by this procedure, as intuitively I would have expected the INSTAT register to be set to 0U to clear interrupt status and to 1U to set interrupt status.
Well, that solves the problem, though it should be maybe considered if not to implement this more intuitively if possible in the future.
Thank you for your help.

Best regards

Philip.

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GPIO_clearBankIntrStatus looks erroneous to me