Other Parts Discussed in Thread: TEST2
Hi all:
I meet a problem when compiling my code if add "CFLAGS+= -D SD_TEST" in Makefile.
The code in my .C file:
#ifdef SD_TEST
test1();
#else
teset2();
#endif
Running result:
when I add CFLAGS+= -D SD_TEST in Makefile, then compiling this .c file without changing other codes, the gcc will not compile this .C file.
The program will still run test2() rather than test1(). Otherwise, when I make clean the whole project, then compile the project again, it will run test1.
What I want to achieve:
1. do not use make clean because it costs long time;
2. when add CFLAGS+= -D SD_TEST in makefile, the program will run test1(), if comment out CFLAGS+= -D SD_TEST， then run test2()
By the way, If I add a "Predefined symbols" in CCS , then compile the code, I find each .c file will be compiled. When I delet the "Predefined symbols" and without changing other codes, the ccs will still compile all .c files. So what's the difference between "ccs build" and normal makefile?
