This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LC4357: TMS570LC4357: MEM5A: Interconnect Partiy Compare Logic Test - Errors

Part Number: TMS570LC4357

Hi experts,

This is a repost to: e2e.ti.com/.../tms570lc4357-mem5a-interconnect-partiy-compare-logic-test

To start MEM5A we set SCMCNTRL[27:24] to Ah.

But the only Errors I observed so far were ESM 1.52, 2.7, 1.70 and one time 2.17.

The Problem is that the technical reference manual states the following:
"The interconnect also output an inverted polarity for output control and address signals. Thus, master and slave IP connected to interconnect could potentially generate parity error as well."

So we need to know every possible error that can get generated by this test, so we can deal with them and will not get a false positive.

(Q) Which errors could potentially occur during MEM5A?

Thank you and best regards,
Max

  • Hi Max,

    (Q) Which errors could potentially occur during MEM5A?

    What I got for interconnect parity compare logic:

    ESM 2.3, ESM 2.7, ESM 2.17, ESM 1.52, ESM 1.70:

    RAMERRSTATUS bit 15 (Command Parity Error on Idle):

    FEDAC_PASTATUS bit 10 (Address Parity Error Flag, get this error only 1 time) and bit 14(Parity Error in idle state):

    FEDAC_PBSTATUS bit 14 (Parity Error in idle state):