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AM2432: PADCONFIG Questions

Mari Tsunoda
Expert 5726 points
Part Number: AM2432

Hi Team,

My customer has a question as below.

1. About RXACTIVE bit and TX_DIS bit of PADCONFIG registers. Is the following recognition correct?
for output signal, TX_DIS=0h, RXACTIVE=0h.
for input signal, TX_DIS=1h, RXACTIVE=1h 

2. I think that RXACTIVE on PADCONFIG register should be set 1h(Receiver enabled) only when the related pad is input signal. But the description about Clock output pad of various block (for example MCSPI, OSPI, MMCSD1), say that it should be set 1h even they are output signals.
Are there other usages like below?
set RXACTIVE=1h even if it's an output port
set RXACTIVE=0h even if it's an input port
set TX_DIS=1h even if it's an output port
set TX_DIS=0h even if it's an input port

Best regards,

Mari Tsunoda

  • 0
    TI__Mastermind 22953 points

    Hello Mari,

    Question has been assigned and we are looking into it, should have an answer before EOW. Thank you for your patience.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 5726 points

    Hi,

    Any update on this?

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Genius 10634 points

    Mari, 

    My apologies for the delay.  

    1. About RXACTIVE bit and TX_DIS bit of PADCONFIG registers. Is the following recognition correct?
      for output signal, TX_DIS=0h, RXACTIVE=0h.
      for input signal, TX_DIS=1h, RXACTIVE=1h 
      1. Yes, this is correct.  Please reference Table 5-4 in the Technical Reference Manual.
    2. I think that RXACTIVE on PADCONFIG register should be set 1h(Receiver enabled) only when the related pad is input signal. But the description about Clock output pad of various block (for example MCSPI, OSPI, MMCSD1), say that it should be set 1h even they are output signals.
      Are there other usages like below?
      set RXACTIVE=1h even if it's an output port
      set RXACTIVE=0h even if it's an input port
      set TX_DIS=1h even if it's an output port
      set TX_DIS=0h even if it's an input port
      1. The signals you mentioned need to be set to 1h due to the loopback clock requirement on the device.

    Regards,

    Brennan

  • 0 in reply to Brennan Hartigan
    TI__Expert 5726 points

    Hi Brennan,

    Thanks for your reply. Could you elaborate on q2 about what you mean by:

    Brennan Hartigan said:
    need to be set to 1h due to the loopback clock requirement

    Intuitively, it seems odd to me that a receiving port is set to 1 when it is an output signal. Also, is this the only situation where the CLKLB affects the RX/TX signals?

    Best regards,

    Mari 

  • 0 in reply to Mari Tsunoda
    TI__Genius 10634 points

    Mari, 

    These signals need to be set t 1h for retiming purposes.  This maintains critical clock to data time requirements on the device.

    Regards,

    Brennan