AM2432: Setting GPMC and DDRSS Clock

Hi Tsunoda-san,

Mari Tsunoda said:

* GPMC=50MHz (FCLK will be MAIN_PLL0_HSDIV3_CLKOUT.)

If using MAIN_PLL0_HSDIV3_CLKOUT as source for the GPMC FCLK, then you would have to first modify the HSDIV3 value and after that adjust the GPMCFCLKDIVIDER value accordingly:

• In register PLL0_HSDIV_CTRL3 (Address 0x0068008C) set HSDIV value to 0x14 (2000MHz/20 = 100MHz).
• In register GPMC_CONFIG1_i (assuming i=0, address 0x3B000060) set GPMCFCLKDIVIDER to 1 (100MHz/2 = 50MHz

Mari Tsunoda said:

* DDRSS=625MHz or 150MHz

DDRSS does not contain any IP level divider blocks so, assuming that they don't want any other changes to their DDR configuration, you will need to adjust the PLL feeding into the DDR itself (MAIN_PLL12_HSDIV0_CLKOUT).

When you say you want DDRSS at 625MHz or 150MHz are you referring to the output frequency of the clock or the DDRSS0_FCLK? The reason I ask this is because for DDR the internal PLL frequency should be running at half of what the expected DDR output rate is. So for example, if you want DDR to be operating with a 625 or 150 MHz output clock then you would need approximately a 312.5 or 75 MHz internal clock respectively. 

Regardless of this, you should be able to modify the PLL input to the DDR by following section 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide of our TRM. Table 5-1352. Programming Sequence of PLLCTRL, HSDIV, and PLL summarizes the full programming sequence and you can take a look at it for quick reference. I don't believe that the values you specified can be achieved by using integer dividers, so I suggest modifying registers PLL12_FREQ_CTRL0 and PLL12_FREQ_CTRL1 in order to obtain the fractional values required to obtain the output clocks you desire.

Best,

Daniel

Link to TRM: www.ti.com/.../spruim2c.pdf