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MSP432E401Y: Contradictory information in reference manual regarding USBRXDPKTBUFDIS

Marc Vuilleumier
Prodigy 70 points
Part Number: MSP432E401Y
Other Parts Discussed in Thread: TM4C123GH6PM

MSP432E4 Technical Reference Manual (Literature Number: SLAU723A) provides contradictory information regarding the bit value of USBRXDPKTBUFDIS

Table 27-73. USBRXDPKTBUFDIS Register Field Descriptions says "0x1 = Enables double-packet buffering"

But the not in paragraph 27.3.1.3.2 Double-Packet Buffering says:

Double-packet buffering is disabled if the corresponding EPn bit of an endpoint is set in the
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering."

So which one is correct ? Should the bit be set or clear to enable double-packet buffering ?

I tried to find the answer by analogy looking at another device, but it looks llike TM4C123GH6PM has the exact same contradiction in the tech manuel...