Other Parts Discussed in Thread: SYSCONFIG
Hi,
I was trying to do some tests of data copy with the DMA from the ADCs on the brand new Sitara AM2634. Naively, I wanted to copy the converted data from the ADC to the DAC and then, being able to measure something with my oscilloscope. The sequence diagram below shows my concept.
The goal is that the DMA copies the ADC0 output to the DAC input at each end of conversion. I kept the basic configuration of the DAC with load mode based on SYSCLK (which is 200 MHz).
The system works pretty well when I configure my timer to generate interrupt at a rate equal or higher than 2 μs. If I try to update the DAC at a higher rate, I get strange behavior: the output of the DAC is only updated each 2 μs and that is independent of my update rate (at least, during my tests). For me, it was clear that the settling time of the DAC is 2 μs and therefore, the DAC would not be able to follow my signal but would anyway be updated, for example, each 1 μs.
So my question is: is there any hardware feature limiting the update rate of the DAC to 2 μs or is it a limitation set by SysConfig and it would be a way to overcome it?
Thank you for your time and answer.
Br, Nicolas
