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TMS570LC4357: What will happen if two master bus access EMIF?

li xy
Intellectual 355 points
Part Number: TMS570LC4357

Hi all:

    In my project, there are two memory devices SDRAM and MRAM  connected to CPU through EMIF with two different "chip select".

    Here is the problem:

    When I access the buf in SDRAM through DMA and at the same time CPU access the buf in MRAM.  What will happen now?  Will there be a fault? such as ESM, hardware fault?

Best Wish

Li

  • 0
    TI__Guru**** 197356 points

    Hi,

    All bus masters (for example CPU, DMA, HTU, etc) on the CPU Interconnect Subsystem have a point to point connection to the EMIF slave. The CPU interconnect subsystem arbitrates between the accesses from multiple bus masters (CPU, DMA, etc) to the bus slaves using a round robin priority scheme.

    The CPU Interconnect Subsystem contains timeout counters to count the amount of time it is taking for a master request to be accepted by the slave and also to count the amount of time it takes from an accepted request to the slave response. When either the request-to-accept counter or the accept-to-response counter expires by the slave, a timeout
    error is asserted to the ESM (ESM 1.92).

  • 0 in reply to QJ Wang
    Intellectual 355 points

    Thank you for your answers QJ. 

    1. I find something about timeout  in TRM and it related to SCMIAERR1STA and SCMIAERR0STAT,etc. However How could I use this function? or Where should I put this function in my project? Could you please provide some demo code?

    2. Will this timeout error cause data abort?

  • 0 in reply to li xy
    TI__Guru**** 197356 points
    li xy said:
    2. Will this timeout error cause data abort?

    No data abort is generated

    li xy said:
    Could you please provide some demo code?

    I don't have any demo code. SCMIAERR0STAT logs the time out error for command request to command accepted, and SCMIAERR1STAT logs the time out error for command request to command response. If any timeout error occurs, you may increase the threshold value. 

  • 0 in reply to QJ Wang
    Intellectual 355 points

    "When threshold compare block triggers a time out error, the error will be sent to the ESM module resulting in an interrupt exception to the CPU."

    1. what's the meaning of  interrupt exception? The interrupt exception is  exception or  interrupt ?

    2. "the error will be sent to the ESM" which channel of ESM will be received? is Channel 91 SCM timeout?

  • 0 in reply to li xy
    TI__Guru**** 197356 points
    li xy said:
    1. what's the meaning of  interrupt exception? The interrupt exception is  exception or  interrupt ?

    Group1 errors have a configurable interrupt response and configurable ERROR pin behavior. If enabled, it will generate ESM high or low interrupt.

    li xy said:
    2. "the error will be sent to the ESM" which channel of ESM will be received? is Channel 91 SCM timeout?

    yes, it is ESM 1.91