Hello,
in the document SPNU495A in Table 14-1 and in 14.9.9 the register offsets for the CPU1_CURMISR[3:0] are given as 0x2C, 0x30, 0x34, and 0x38, however I think that this is not correct and they are in fact 0x1C, 0x20, 0x24, and 0x28.
Could you please confirm this and take it into account for the next update of this document.
Best regards
Andreas
