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TMS570LC4357: N2HET PWM period error

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

王工您好:

       我现在使用N2HET功能,产生PWM,周期为1000us。如果VCLK2配置为75M,则用示波器读取脉冲周期正确。如果VCLK2配置为50M,则示波器读取脉冲错误,请问这是为什么错啊。

       

int main(void)
{
/* USER CODE BEGIN (3) */
hetInit();
pwmStart(hetRAM1,0);

/* USER CODE END */

return 0;
}

     VCLK2配置为75M时,示波器显示周期正确,1000us。

     

    VCLK2配置为50M时,示波器显示周期错误,666us。

   

    

  • After you changed the VCLK, did you re-generate N2HET code? The data field of DJZ and MOV64 should be updated.

  • 王工,我重新生成代码了,你可以做个实验试一下嘛

  • 1. NHET configuration for VCLK=50MHz:

    PWM code for VCLK=50MH

    Data field of the instructions are:: 99968 (period, instruction 42), and 50176 (duty, instruction 41)

    The period = 1280ns * (99968 >> 7) =1280*781= 999.68us

    2. NHET Config for VCLK=75MHz

    PWM code for VCLK=75MH

    Data field of the instructions are: 149888 (period, instruction 42), and 75136 (duty, instruction 41)

    The period = 853.333ns * (149888 >> 7) = 853.33ns *1171=999.249us

    So both PWMs have the same period.

  • 王工:

           我们50M时钟时,生成的代码跟您的一样,但是产生的脉冲的确不对。设计是1000us,但实际是667.3us。您方便用您的工程,实际接上示波器看一下

    您那边在50M时钟下,的确生成了1000us吗?我们用的是N2Het1[17]这个引脚。

  • 王工:

          还有个问题咨询一下。

        1)N2HET1[17] 引脚可以采集pwm脉冲的周期和占空比吗?是不是只有偶数的引脚才能采集pwm周期和占空比?

        2)N2HET1[18] 引脚采集pwm脉冲的周期和占空比,是不是必须N2HET1[19] 设置为HR Share,这样配合来采集?

         3) 如果N2HET1[19] 设置为HR Share和N2HET1[18] 配合采集脉冲,那么N2HET1[19] 可以设置成输出引脚吗?

         

  • 设计是1000us,但实际是667.3us

    I guess your N2HET code is generated for 50MHz VCLK (period=99965, duty=50176), but the VCLK2 used in your code is still 75MHz.

    Please check the VCLK2 divider in system CLKCNTL register.

    My setting GCLK=300 --> HCLK=150-->VCLK2=HCLK/3 = 50MHz

    I don't have a scope at home. 

    There are two balls for N2HTE1[17] : F3 and A13. 

  • 王工:

            我看了一下手册,The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The VCLK2 frequency must be an integer multiple of the VCLK frequency。

            所以如果VCLK2配置成50M,但VCLK1还是75M的话,是错误的。

            我将VCLK1也改成50M,VCLK2配置成50M,但是1000us的脉冲周期还是667us,您知道这是哪里的问题吗?将VCLK1配置成25M,VCLK2配置成50M,PWM输出是正确的。

            此外,您能回复一下上述关于N2HET1[17] 、N2HET1[18] 、N2HET1[19] 的咨询吗,谢谢。

  •   1)N2HET1[17] 引脚可以采集pwm脉冲的周期和占空比吗?是不是只有偶数的引脚才能采集pwm周期和占空比?

    Yes, but only one of them has high resolution. The PCNT instruction is used to capture period and duty cycle.

    The N2HET supports high resolution and standard resolution. The N2HET instruction such as PCNT used for edge capture (CAP) has 7-bit HR data field. For standard resolution, the 7-bit HR data is ignored. For high resolution, the 7-bit HR data can measure high resolution delays (HR delay). But the restriction is that only one instruction is allowed to operate in High Resolution mode for a N2HET pin. 

    The example code generated by HALCoGen enables the HR share, both PCNT instructions for period and duty-cycle operate in high resolution mode. The first PCNT uses the HR structure of pin (n) (even number), and the 2nd PCNT uses the HR structure of pin (n+1) (odd number). The input signal must be connected to pin (n). 

    The HAL code assumes the signal is connected to pin (n), so the HR of pin (n) (Even number) is used for duty cycle, and the HR of pin (n+1) is used for the period. If the input signal is connected N2HET1[17], you will not get correct duty cycle and period using the HALCoGen generated code. 

    But you can write your own code to capture duty cycle and period of the signal connected to N2HET1[17], but one of the PCNT instructions can not use high resolution.

  • 2)N2HET1[18] 引脚采集pwm脉冲的周期和占空比,是不是必须N2HET1[19] 设置为HR Share,这样配合来采集?

    Yes, your understanding is correct. 

    3) 如果N2HET1[19] 设置为HR Share和N2HET1[18] 配合采集脉冲,那么N2HET1[19] 可以设置成输出引脚吗?

    N2HET1[19] can be used as GIO input or output.

  • 我看了一下手册,The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The VCLK2 frequency must be an integer multiple of the VCLK frequency。

            所以如果VCLK2配置成50M,但VCLK1还是75M的话,是错误的。

    Excellent you solved the issue. Thanks