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RM57L843: Erase, program and read back the flash with cache enable/disable

Part Number: RM57L843

Hello TI engineer:

    In boot mode of my application, when in the bootloader mode, MPU is disabled successfully. But when the cacheDisable function as shown followed is called,  the MCU abnormal and fly.

;-------------------------------------------------------------------------------
; Disable caches

        .def  _cacheDisable_
        .asmfunc

_cacheDisable_

        stmfd sp!, {r1}

        MRC   p15, #0, R1, c1, c0, #0   ; Read System Control Register configuration data
        BIC   R1, R1, #0x1 <<12         ; instruction cache disable
        BIC   R1, R1, #0x1 <<2          ; data cache disable
        DSB
        MCR   p15, #0, R1, c1, c0, #0   ; disabled cache RAMs
        ISB

        ldmfd sp!, {r1}

        bx    lr
        .endasmfunc

 After trying  erase, program and read back the flash with cache enable, I found the erase and program may be OK, but the read back contents are random.

I guess that the read will read from the cache memory instead of the Flash.

Q:

1) How to disable the cache?

2) Can I run the bootloader with cache enable? How to fix the read back problem?

Thank you.

  • 1) How to disable the cache?

    Calling _cacheDisable_() to disable the cache. The function should be called in no-user mode. 

    2) Can I run the bootloader with cache enable? How to fix the read back problem?

    Yes, you can. You can define a section for the readback data. The section should be configured as write through instead of write back.

    Linker scrip:

     SHAREDRAM (RW) : origin=0x0807F000 length=0x00001000

        .sharedRAM : {} > SHAREDRAM

    in main():

    #pragma SET_DATA_SECTION(".sharedRAM")
       uint8_t TX_DATA[size] = {0};
       uint8_t RX_DATA[size] = {0};
    #pragma SET_DATA_SECTION()