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AM263x cc EVM SBL _ SPI master + DMA

carmel gorali
Prodigy 50 points

Hi!

I'm working with SPI - master mode  and DMA.

I configured the following:

- DMAW in CH0CONF

- DMAR  in CH0CONF

- Configured the relevant DMA channels and XBAR

What I see (using scope) that there are a delay's  between WORDs transmitted.

Is there a way to use DMA and FIFO? I see in register "XFERLEVEL" that the DMA can get event in case the FIFO is almost empty:

AEL bit 0-7 : Buffer Almost Empty This register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the buffer MCSPI_MODULCTRL[AEL] must be set with n-1"

I also see that "DMAW " description "DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel"

Is there any way to eliminate the delay between words ?

Thanks

Carmel

  • +1
    TI__Guru 54875 points

    Hi Carmel,

    There is an known issue with the McSPI driver which cause a delay before and after each transfer. One way to reduce the delays before and after each transfer. You can use the following method:

    The FORCE bit (bit 20) in MCSPI_CHCONF_0 allows the manual control of the CS. If you are using the McSPI DMA API from MCU+ SDK, the spiTransaction.csDisable and spiTransaction.csEnsable need to be set properly.

    I see different ways to handle the FORCE bit in MCU+ SDK examples:

    1. mcspi_loopback.c and mcspi_loopback_dma.c set the spiTransaction.csDisable = TRUE
    2. mcspi_performance_32bit.c and mcspi_performance_8bit.c use MCSPI_writeChConfReg(baseAddr, chNum, gCsAssertRegVal) to set the FORCE bit directly.

    Make sure you do not enable the FORCE bit in MCSPI_CHCONF_0.

    Best regards,

    Ming