• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 33 subscribers
  • Views 818 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2634: PRU interrupt management

Nicolas B.
Prodigy 180 points
Part Number: AM2634
Other Parts Discussed in Thread: DRA829

Hi,

I would like to work with interrupts on the PRUs of Sitara AM2634. Looking on E2E, I understood that prior to DRA829 and AM65 series, the PRU's interrupt controller was a mapping of interrupt sources (from ICSS and System on Chip) to a register. Then, I was expecting to get something similar on AM2634. But looking at the TRM, chapter 7.2.6, it is peaking about nested interrupts. So I wonder if the INTC of PRUs on AM2634 is implementing a interrupt reaction?

Furthermore, is there any example how to use interrupts on PRU with reaction?

Thank you and Best Regards.

Nicolas

  • 0
    TI__Mastermind 29738 points

    Hi,

    Sorry for the delayed response. I'm looking into this and will get back with you.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    TI__Expert 7245 points

    Hello Nicolas,

    To clarify, are you wanting to learn about capture system events as interrupt inputs for the PRU or generate PRU interrupts for other cores? Chapter 7.2.6.1 explains how the interrupt controller works for the PRU subsystems of the AM263x.

    For a list of the interrupt sources for the PRU refer to chapter 10.4.5 "PRU_ICSSM0 Interrupt Map". This table will list the interrupt lines of the PRU and each interrupt's source. 

    We currently do not have any examples of using PRU interrupts with reaction. 

    In order to see the interrupts within a register, you must poll the register of the ICSS INTC that correlates to the N-th bit of the INTC Status register where n is the interrupt number from the PRU_ICSSM0 Interrupt Map. For more information on checking the status of a pending interrupt refer to chapter 7.2.6.1.2.2 "PRU_ICSSM Interrupt Status Checking". The ICSS_INTC registers are not currently in the AM263x register addendum but here is a list of the INTC registers and their physical address in memory. 

    Register Name Physical Address
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_REVISION_REG (0x00020000U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CONTROL_REG (0x00020004U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_GLOBAL_ENABLE_HINT_REG (0x00020010U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_GLB_NEST_LEVEL_REG (0x0002001CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_STATUS_SET_INDEX_REG (0x00020020U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_STATUS_CLR_INDEX_REG (0x00020024U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_SET_INDEX_REG (0x00020028U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_CLR_INDEX_REG (0x0002002CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_HINT_ENABLE_SET_INDEX_REG (0x00020034U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_HINT_ENABLE_CLR_INDEX_REG (0x00020038U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_GLB_PRI_INTR_REG (0x00020080U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_RAW_STATUS_REG0 (0x00020200U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_RAW_STATUS_REG1 (0x00020204U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENA_STATUS_REG0 (0x00020280U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENA_STATUS_REG1 (0x00020284U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_REG0 (0x00020300U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_REG1 (0x00020304U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_CLR_REG0 (0x00020380U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_CLR_REG1 (0x00020384U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG0 (0x00020400U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG1 (0x00020404U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG2 (0x00020408U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG3 (0x0002040CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG4 (0x00020410U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG5 (0x00020414U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG6 (0x00020418U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG7 (0x0002041CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG8 (0x00020420U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG9 (0x00020424U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG10 (0x00020428U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG11 (0x0002042CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG12 (0x00020430U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG13 (0x00020434U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG14 (0x00020438U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_CH_MAP_REG15 (0x0002043CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_HINT_MAP_REG0 (0x00020800U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_HINT_MAP_REG1 (0x00020804U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_HINT_MAP_REG2 (0x00020808U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG0 (0x00020900U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG1 (0x00020904U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG2 (0x00020908U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG3 (0x0002090CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG4 (0x00020910U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG5 (0x00020914U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG6 (0x00020918U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG7 (0x0002091CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG8 (0x00020920U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_PRI_HINT_REG9 (0x00020924U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_POLARITY_REG0 (0x00020D00U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_POLARITY_REG1 (0x00020D04U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_TYPE_REG0 (0x00020D80U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_TYPE_REG1 (0x00020D84U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG0 (0x00021100U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG1 (0x00021104U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG2 (0x00021108U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG3 (0x0002110CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG4 (0x00021110U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG5 (0x00021114U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG6 (0x00021118U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG7 (0x0002111CU)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG8 (0x00021120U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_NEST_LEVEL_REG9 (0x00021124U)
    CSL_ICSS_M_PR1_ICSS_INTC_SLV_ENABLE_HINT_REG0 (0x00021500U)

    Regards,

    Erik 

  • 0 in reply to Erik Friedel
    Prodigy 180 points

    Hi Erik,

    thank you for your answer, my question was about getting interrupts/events to the PRU. Generating interrupts from PRU to other cores will come later for me.

    Okay, then, that clear for me that, I have to configure the ICSS to map a "Sys_Event" to one of the 10 channels and then, I can, for example, link up to the 10 channels to the Host-0 to get the interrupt in register R30, bit 30 of both PRU0 and PRU1. To get the highest-priority pending interrupt, I read the register ICSS_INTC_GLB_PRI_INTR_REG and I can execute my interrupt routine.

    What blurred me is the chapter 7.2.6.1.2.4 PRU_ICSSM Interrupt Nesting of the TRM. Does the topic "interrupt nesting" here is just an hardware masking of lower priority interrupts until the interrupt was cleared or does it mean that there is a "context switching" to an interrupt routine in PRU (like on Cortex-R5F)?

    Thank you again for your answer.

    Best Regards, Nicolas

  • 0 in reply to Frank Livingston
    Prodigy 180 points

    Hi Frank,

    No problem. Thank you to have taken the time.

    Br, Nicolas

  • 0 in reply to Nicolas B.
    TI__Expert 7245 points

    Hello Nicolas,

    In order for the INTC to generate an interrupt, the corresponding system event bit must be enabled and, once enabled, the system event status will be reflected in the Status register. Status of interrupt 'N' is indicated by the N-th bit of ICSS_INTC_ENA_STATUS_REG0 to ICSS_INTC_ENA_STATUS_REG4. Since there are 160 interrupts, five 32-bit registers are used to capture the enabled status of interrupts. Then, enabled interrupts can be mapped to one of the 10 internal channels of the INTC where Channel 0 has the highest priority and channel 9 has the lowest priority. By enabling interrupt nesting, you are disabling lower priority interrupts (channels) while an interrupt is being serviced. This then allows the host to service the current interrupt and only allow higher priority interrupts to trigger to the host. 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 180 points

    Hi Erik,

    thank you for your answer. It answers my questions!

    Have a nice day.

    Br, Nicolas