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RM46L852: Dual spi slave issue

Part Number: RM46L852
Other Parts Discussed in Thread: HALCOGEN,

Hello everyone !

I developped a slave spi interface which is working and now I need another one. The fact is that with the same configuration, the same code structure it is not working. I checked the hardware and it is not comming from there.

The main difference is coming from the delay between bytes (sended by a MSP430). Another thing, I use SP1 and SP4 for the slaves interfaces and when I look at the file spi.c I see that HALCOGEN generated SPI1 interrupts as MIBSPI and SPI4 as SPI4 interrupt. Could the issue coming from there ?

In debug mode if I put breakpoints in MIBSPI1 and SP14 interrupts It stops in mibspi1HighLevelInterrupt (only that one at the call of spiSendAndGetData which seems ok because no data is sended on this slave for now) for Transmit Buffer Empty and nowhere in spi4LowLevelInterrupt and spiHighLevelInterrupt.

Here is my Halcogen project and a picture of the spi signal sended by the MSP430 master.

RM46L852_HALCOGEN.zip

Any idea would be helpful !

Best Regards,

Fabian

  • Hi Fabian,

    I am reading your code, and come back to you later.

  • The attachment is just a HAL generated driver. I don't find your code. 

    I noticed that the SPI clock phase is enabled. Is this required by the SPI master? if the phase is enabled, the data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. The input data is latched on the rising edge of SPICLK.

    The SPI master must provide the SPI clock for SPI slave to transmit and receive data.

  • Hello,

    Thanks for your reply !

    I didn't put the code in folder sorry. Here is my state machine used. :

           switch (state_machine) {
            case MSP430_STATE_MACHINE_COMMUNICATION_END :
                previous_state_machine = MSP430_STATE_MACHINE_COMMUNICATION_END;
                state_machine = MSP430_STATE_MACHINE_WAIT_FOR_COMMAND;
                gpio_set(msp430_interface_params->msp430_slave_ready_gpio, 0U);
                vTaskDelay(pdMS_TO_TICKS(msp430_interface_params->task_period));
                break;
            case MSP430_STATE_MACHINE_WAIT_FOR_COMMAND :
                previous_state_machine = MSP430_STATE_MACHINE_WAIT_FOR_COMMAND;
                memset(&MSP430_DATA_RX[0], 0x00, sizeof(MSP430_DATA_RX[0]) * MSP430_DATA_SIZE);
                memset(&MSP430_DATA_TX[0], 0x44, sizeof(MSP430_DATA_TX[0]) * MSP430_DATA_SIZE);
                //spi_slave_transfer(msp430_interface_params->msp430_spi_slave_handle, &MSP430_DATA_RX[0], &MSP430_DATA_TX[0], MSP430_FRAME_SIZE_COMMAND_LENGTH);
                spiSendAndGetData(spiREG4, &msp430_spi_slave_config, 1, &MSP430_DATA_RX[0], &MSP430_DATA_TX[0]);
                gpio_set(msp430_interface_params->msp430_slave_ready_gpio, 1U);
                msp430_slave_delay = 0;
                while((SpiRxStatus(spiREG4) != SPI_COMPLETED) && (msp430_slave_delay < APP_MSP430_DELAY_MAX)) {
                    msp430_slave_delay++;
                }
                if(msp430_slave_delay == APP_MSP430_DELAY_MAX) {
                    state_machine = MSP430_STATE_MACHINE_COMMUNICATION_END;
                }
                else if((MSP430_DATA_RX[MSP430_COMMAND_FRAME_INDEX_START_OF_COMMUNICATION] == MSP430_FRAME_VALUE_START_OF_FRAME)
                        && (MSP430_DATA_RX[MSP430_COMMAND_FRAME_INDEX_END_OF_COMMUNICATION] == MSP430_FRAME_VALUE_END_OF_FRAME)) {
                } else {
                    state_machine = MSP430_STATE_MACHINE_COMMUNICATION_END;
                }
                break;
            case MSP430_STATE_MACHINE_SEND_STATUS :
                previous_state_machine = MSP430_STATE_MACHINE_SEND_STATUS;
                state_machine = MSP430_STATE_MACHINE_COMMUNICATION_END;
                break;
            default:
                state_machine = MSP430_STATE_MACHINE_COMMUNICATION_END;
                break;
            }

    with :

    spi_config_t msp430_spi_slave_config = {
         .CS_HOLD = FALSE, .WDEL = FALSE, .DFSEL = SPI_FMT_0, .CSNR = SPI_CS_0};

     > I noticed that the SPI clock phase is enabled. Is this required by the SPI master?

    No it's not required by the MSP430 but I chose to keep the configuration of the other slave.

    Best regards,

    Fabian

  • I developped a slave spi interface which is working and now I need another one.

    Does the SPI slave using RM46Lx work before? 

    Have you enabled the interrupt (IRQ)? 

    How do you guarantee that the spiSendAndGetData() is called before the SPI master transmit data to slave?

  • Does the SPI slave using RM46Lx work before? 

    Yes It does and this is on the same chip that I want to implement the second SPI slave.

    Have you enabled the interrupt (IRQ)? 

    Yes I have.

    How do you guarantee that the spiSendAndGetData() is called before the SPI master transmit data to slave?

    On the code I provided there is signal called slave_ready telling the master that the slave is ready to receive data. So It ensure that the slave call spiSendAndGetData() before the master send data.

    Is it possible to have multiple slave on the same device ? I think so but I prefer to ask.

    I use also FREERTOS can it have an impact ?

    Best regards,

    Fabian

  • Is it possible to have multiple slave on the same device ?

    Yes, you can connect as many slave as the number of chip-select pins of the SPI master. For example, if the MSP430 SPI module has 4 nCS pins, you can connect 4 slaves to this SPI module.

    I use also FREERTOS can it have an impact ?

    It should be fine to use SPI under freeRTOS.