TMS570LS1114: External SDRAM access issue using RTOS

Hi Konstandy，

Is the SDRAM function called in a task? Is there any interrupt ISR called periodically during writing data to SDRAM?

Is IRQ enabled when writing data to SDRAM in your main() without RTOS?

Hi QJ Wang,

- My shown example is called from one of the runnings tasks.

- We use many other routines that could well use the interrupt (e.g. MIBSPI, CAN...).

- For the test from the main() the same interrupts are activated as during the OS operation. However, the SDRAM is used directly after the call of the _mpuInit_() in the main() with the same example as shown in attached screenshots.

The byte write uses strb instruction, I don't know how it is interrupted by other IRQ ISR. Does the data delay time and hold time of the SDRAM meet the EMIF specification listed in device datasheet?

The parameters were set according to the data sheet (we use IS42S16100H-7) in Halcogen. Writing to the SDRAM without the OS or with interrupts turned off works without problems, so I assume that the parameters are correct. 

Is there anything else I'm missing that could affect the SDRAM through the influence of taskENTER_CRITICAL and taskEXIT_CRITICAL? 

Hi,

I am not an expert of freeRTOS, so I am not sure how freeRTOS impacts the SDRAM accesses. 

Konstanty Kuczynski1 said:

Is there anything else I'm missing that could affect the SDRAM through the influence of taskENTER_CRITICAL and taskEXIT_CRITICAL? 

Which silicon revision is your TMS570LS1114 device?

TMS570LS12x/11x Microcontroller Silicon Errata (Silicon Revision B) (Rev. F) has errata DEVICE#B064:

Looking at the FreeRTOS os_portasm.asm assembler source file provided with HALCoGen shows the assembler using store multiple STMxx instructions, so maybe the FreeRTOS context switching code could trigger errata DEVICE#B064.

That errata is marked as fixed in TMS570LS12x/11x Microcontroller Silicon Errata (Silicon Revision C) (Rev. C)

We are using revision C - TMS570LS1114CZWTQQ1.