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TMS570LC4357: ADC10 Parity Bits memory mapping not clear

Max Wittekind
Expert 1835 points
Part Number: TMS570LC4357

Hi experts,

The diagnostic ADC10 listed in the Safety Manual suggests testing the parity logic of the ADC. I found the function SL_SelfTest_ADC() and we used it as reference for our implementation.

According to the Reference Manual the Parity bits are memory mapped when the testmode is active. For the dataword at Adress 0xFF3E0000 the parity bit should be at 0xFF3E0000 + 0x1000.
What is missing is a description how to find the parity bits for each word in the memory.

Let's say I wanted to flip a Parity bit for the word at address 0xFF3E0000 how do I know which bit to flip at 0xFF3E0000 + 0x1000?

Lookin at the test function in the SafeTi Lib, it suggests flipping the parity bit at the following address:

#define adc1RAMParLoc ((volatile uint8 *)(0xFF3E0007U + 0x1000U))

and read the word at

#define adc1RAMLoc   ((volatile uint32 *)0xFF3E0004U)

(Q1) How do I know that the Adress adc1RAMParLoc maps to the parity bit for the word at 0xFF3E0004U?

(Q2) Why do I need a 8bit acces when the Technical Reference states that ADC RAM only supports 32bit access?

What I find interesting, is that flipping a bit at 0xFF3E0006U + 0x1000U and 0xFF3E0004U + 0x1000U also works.

Thank you and best regards,
Max

  • 0
    TI__Guru**** 192146 points
    Max Wittekind said:
    how do I know which bit to flip at 0xFF3E0000 + 0x1000?

    It is the least significant bit. 

    The parity for the value at 0xFF3E0028 is the least significant bit of the value at 0xFF3E1028 (0xFF3E0028+0x1000).

    Max Wittekind said:
    is that flipping a bit at 0xFF3E0006U + 0x1000U and 0xFF3E0004U + 0x1000U also works.

    The value at 0xFF3E0006U + 0x1000U should not be flipped. It is always 0x0. It is 4-byte aligned. 

    Max Wittekind said:
    (Q1) How do I know that the Adress adc1RAMParLoc maps to the parity bit for the word at 0xFF3E0004U?

    You can modify the value at 0xFF3E0004 (flip 1 bit), and check if the lsb at 0xFF3E1004 changes.

    Max Wittekind said:
    (Q2) Why do I need a 8bit acces when the Technical Reference states that ADC RAM only supports 32bit access?

    The datasheet says that only 32-bit reads and writes are allowed to the ADC results’ RAM in test mode. So I suggest to do 32-bit access instead of 8-bit. 

  • 0 in reply to QJ Wang
    Expert 1835 points

    Hi QJ,

    Flipping the LSB works for me only with an 8Bit access to Parity Ram, if I try it with a 32bit access nothing happens.

    Does the Parity Ram only support 8bit access?

    Also, the Reference Manual suggest, there are 2 parity bits for a 32bit word (1bit for 16bits of data) (Chapter 22.2.7.3), but when looking at the Parity Ram with a debugger it looks like there is only 1 Parity for a 32bit word. Is this an error in the reference Manual?

  • 0 in reply to Max Wittekind
    TI__Guru**** 192146 points
    Max Wittekind said:
    Does the Parity Ram only support 8bit access?

    Actually we can perform 8-bit access or 32-bit access from my test.. The TRM is not accurate. There is 1 parity bit for 32-bit word or 17-bit (the upper 15 bits are reserved, and won't affect the parity).

    I need to double check it.

    My test code:

    #define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
    #define adcRAM1_B0 (*(volatile uint8 *)(0xFF3E0000U + 0x3U))

    #define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
    #define adcPARRAM1_B0 (*(volatile uint8 *)(0xFF3E0000U + 0x1000U + 0x3U))

    void adc_parity_test()
    {
             volatile uint32 adcramread = 0U;
             uint32 adcparcr_bk = adcREG1->PARCR;

    /* USER CODE BEGIN (61) */
    /* USER CODE END */

    adcInit();

    adcREG1->OPMODECR &= 0x7FFEFFFF;
    adcREG1->OPMODECR |= 0x80010000; //12-bit (bit 31), ADC RAM Test Mode is enabled(bit 16)

    /* Set the TEST bit in the PARCR and enable parity checking */
    adcREG1->PARCR = 0x10AU;

    adcRAM1 = ~(adcRAM1); //flip all the bits
    adcRAM1 = ~(adcRAM1); //flip all the bits back
    adcRAM1_B0 = ~(adcRAM1_B0); //flip the bits of least byte
    adcRAM1_B0 = ~(adcRAM1_B0); //flip the bits of least byte back

    /* Invert the parity bits inside the ADC1 RAM's first location */
    adcPARRAM1 = ~(adcPARRAM1);
    adcPARRAM1_B0 = ~(adcPARRAM1_B0); //invert lsb
    adcPARRAM1_B0 = ~(adcPARRAM1_B0);

    /* clear the TEST bit */
    adcREG1->PARCR = 0x00AU;

    /* This read is expected to trigger a parity error */
    adcramread = adcRAM1;

  • 0 in reply to QJ Wang
    Expert 1835 points

    Hi QJ,

    So there is a mistake in TRM and we can proceed to just flip the LSB in Partiy RAM safely with an 8bit access?

  • 0 in reply to Max Wittekind
    TI__Guru**** 192146 points

    Hi Max,

    From my test, I think the statement of "Only 32-bit reads and writes are allowed to the ADC results’ RAM in this test mode." is not correct. Can you access the memory in 8-bit mode?

  • 0 in reply to QJ Wang
    Expert 1835 points

    Hi QJ,

    Yes, an 8-bit access and flipping the LSB seems to work.

  • +1 in reply to Max Wittekind
    TI__Guru**** 192146 points

    Thanks Max. I will double check with the owner of this document, then file a litbug.