Hi
How to understand the statement in the datasheet about the UART:
'when last bit of all transmitted data leaves the serializer' (when EOT bit in UART Control register is set)? Does this mean once EOTRIS is set, the BUSY flag in the UART Flag (UARTFR) register will be cleared?
The reason I am asking is that, I am trying to send a data packet via UART with DMA, and as soon as the packet transmission completes, I want to send a special character 9-bit mode. I am using the function UART9BitAddrSend() function in TivaWare. This function would wait till the FIFO is empty and the transmitter is not busy before the special character can be sent.
I am using DMATX to trigger an UART interrupt. In the ISR, this function is called to send the special character. What I noticed is that this interrupt is triggered a bit earlier so that the UART9BitAddrSend() has to wait for a while before the character can be sent. The function is wait for transmitter's idle state. I guess what happened is that, when DMATX is triggered, it only means all the data has sent to FIFO. It still needs some time for the FIFO to be emptied.
I tried to use TX (with EOT set to 1) as the interrupt source instead of DMATX, hoping the interrupt can happen when all the data and the last bit has left the serializer. This should avoid the wait time by UART9BitAddrSend(). But this did not help me. UART9BitAddrSend() still wasted about 40us (UART at 250Kbps) before the special character can be sent.
I am wondering if I correctly understand the statement 'TXRIS is set when the last bit of all transmitted data leaves the serialize'. Doesn't it mean when the interrupt triggers, the transmitter should have finished all the job and become idle so that the function UART9BitAddrSend() can send the character immediately?
Thanks,
Tianlei
