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DMA and MCRC Timing



Hi,

A simple question for you.

If I use a DMA to stream data into MCRC channel 1 and from that first DMA chain a second DMA to stream data into MCRC channel 2, can it be guaranteed that MCRC channel 1 compression complete interrupt will always occur before MCRC channel 2 compression complete interrupt?

Regards, Tony.

  • Hi Tony,

    I am assuming following

    1) You are using Smi-CPU mode in CRC., i.e after compression user goes and compares the signature value
    2) Chaining after Frame or Block transfer
    3) Source for DMA channels are from system RAM.

    Ideally Ch1 compression complete Interrupt should occur before Ch2 compression complete interrupt. I could not thionk of any corner cases that might cause issue.

    Are you facing some issue with this configuration?

    - Prathap

     

  • Hi Prathap,

    Assumptions 1 and 2 are correct. Regarding 3:

    • In one of my cases, one source is from SPI 1 TXRAM and is transferred to MCRC channel 1, the other source is SPI 2 TXRAM and is transferred to MCRC channel 2.
    • In my other case, both sources are from system RAM.

    I don't have any issues with this configuration, I would just like to rely on it. I am triggering an FIQ from MCRC channel 2 compression complete in which I will process both MCRC channel 1 and channel 2 signatures.

    Regards, Tony.

  • Hi Tony,

    Your configuration should work fine. Pls let us know if you have any further questions.

    Best Regards
    Prathap

     

  • Hi Prathap,

    On my setup, it seems as though I can't rely on the order of operation. I get many overrun conditions on the MCRC sector signature register.

    I have re-organised my implementation so that each channel's compression complete is handled independently, this is then 100% reliable with no overruns.

    Thanks for your input, Tony.